Stacked Resistor Electrode Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
The miniaturization of resistance elements in semiconductor devices leads to an increase in parasitic capacitance between electrodes, hindering the increase in speed and reduction in power consumption due to reduced distances between extraction electrodes.
Innovation Solution
A semiconductor device configuration with electrodes in contact with different surfaces of the resistance layer, reducing parasitic capacitance by maintaining electrode distance and allowing for adjustable resistance values through layered structures with varying resistivity, including cermet layers and dual damascene wires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If resistance elements are miniaturized to increase integration density, then device functionality is improved, but parasitic capacitance between electrodes increases due to reduced distance
Solution Approach 1:
The patent transitions from a planar electrode arrangement to a three-dimensional stacked configuration. The first electrode contacts the lower surface of the resistance layer while the second electrode contacts the upper surface, utilizing the vertical dimension to increase electrode separation distance. This dimensional change effectively reduces parasitic capacitance between electrodes while maintaining compact horizontal footprint, thereby preserving integration density.
2Speed
If electrode distance is increased to reduce parasitic capacitance, then speed and power consumption are improved, but device area increases
Solution Approach 1:
The invention resolves the area-speed tradeoff by implementing the electrode separation in the vertical dimension rather than the horizontal plane. The stacked configuration with electrodes on opposite surfaces of the resistance layer achieves large electrode distance without increasing lateral device footprint, thus maintaining small device area while improving operation speed through reduced parasitic capacitance.
Data Source
AI summary
To provide a semiconductor device with which it is possible to reduce parasitic capacitance between electrodes for a resistance element, and a method for manufacturing the semiconductor device. A semiconductor device according to the present disclosure includes: a substrate; a first resistance layer provided on the substrate; a first electrode in contact with a lower surface of the first resistance layer; and a second electrode in contact with an upper surface of the first resistance layer.