Stacked Resistor Structure for High Resistance in MOS Integration
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Solution Overview
Problem
Conventional resistor devices in semiconductor ICs, made of lightly doped polysilicon, face reduced resistance and efficiency when integrated with metal-oxide-semiconductor (MOS) transistor devices, leading to compromised performance in modern electronic products that require increased resistance and efficiency.
Innovation Solution
A semiconductor device structure is developed with a resistor comprising a substrate, a first dielectric layer, a metal layer, and a semiconductor layer sequentially stacked, where a second dielectric layer separates the metal and semiconductor layers to increase resistance, while maintaining the efficiency of MOS transistor devices by not forming the dielectric layer in the gate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a polysilicon layer is formed on a metal layer to integrate resistor and MOS transistor, then the integration efficiency is improved, but the resistance of the resistor is reduced
Solution Approach 1:
The patent segments the resistor structure into multiple functional layers: a metal layer (first layer) and a polysilicon layer (second layer) separated by a dielectric layer. This segmentation allows the metal layer to provide low contact resistance while the polysilicon layer maintains high resistance, resolving the contradiction between integration efficiency and resistor resistance.
Solution Approach 2:
The patent introduces a dielectric layer as an intermediary between the metal layer and polysilicon layer. This dielectric layer acts as a mediator that electrically isolates the two conductive layers, preventing direct contact and thus maintaining high resistor resistance while still allowing both layers to be integrated in the same device structure.
2Reliability
If the resistance of the resistor is increased, then the efficiency of the resistor is improved, but the integration with MOS transistor becomes more difficult
Solution Approach 1:
The patent creates a multi-functional structure where the stacked metal-polysilicon-dielectric configuration serves multiple purposes: the metal layer provides low-resistance contacts, the dielectric layer provides electrical isolation, and the polysilicon layer provides high resistance. This universal structure can be applied to both resistor regions and MOS transistor gate regions, simplifying the overall manufacturing process while maintaining high resistor efficiency.
Data Source
AI summary
A semiconductor device structure including a substrate, a resistor, and a first gate structure is provided. The substrate includes a resistor region and a metal-oxide-semiconductor (MOS) transistor region. The resistor is disposed on the substrate within the resistor region. The resistor includes a first dielectric layer, a metal layer, a second dielectric layer, and a semiconductor layer sequentially stacked on the substrate. The first gate structure is disposed on the substrate within the MOS transistor region. The first gate structure includes the first dielectric layer, the metal layer, and the semiconductor layer sequentially stacked on the substrate.