Stacked RF Die Package With GSG Pads for Millimeter-Wave Grounding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing RF circuit technologies face challenges in integrating high-power millimeter-wave signals due to difficulties in providing a well-defined RF ground reference and limited integration of digital logic circuits with III-V semiconductor-based processes.
Innovation Solution
The solution involves stacking a silicon-based RF chip with an III-V semiconductor-based die, where the III-V die has a backside GND layer and through-substrate GND vias for a well-defined ground reference, and the silicon-based die includes a guard ring connected to ground bumping pillars for grounding. This configuration enables smooth RF signal transmission and high-power output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If silicon-based processes are used for high integration, then digital logic circuits and analog/RF circuits can be combined in a single chip, but it is very difficult and expensive to provide a backside ground plane with through-substrate-via integration
Solution Approach 1:
The invention divides the RF circuit system into two separate dies: a silicon-based die for digital logic and analog circuits, and an III-V semiconductor die for high-power RF amplification. This segmentation allows each die to be optimized for its specific function, with the III-V die providing the backside ground plane capability that is difficult to achieve in silicon-based processes.
Solution Approach 2:
The invention introduces bumping pillars as intermediary connection elements between the silicon-based die and the III-V semiconductor die. These bumping pillars provide electrical connection and mechanical bonding, enabling the two different semiconductor technologies to work together while maintaining the ground reference capability provided by the III-V die's backside ground plane.
2Power
If III-V semiconductors are used for high-power output, then saturated output power exceeds 15 dBm, but it is very difficult to integrate digital logic circuits and basic analog circuits
Solution Approach 1:
The system segments the circuit functions by placing digital logic and analog circuits on the silicon-based die, while the III-V semiconductor die is dedicated to high-power RF amplification. This segmentation enables high-power output while maintaining integration capability through the separation of concerns.
Solution Approach 2:
The bumping pillars serve as intermediaries that connect the silicon-based die (containing digital logic and analog circuits) with the III-V semiconductor die (providing high-power RF output). This intermediary connection enables the integration of circuits that would otherwise be incompatible on a single die.
3Speed
If silicon-based processes are used for high integration, then ft/fmax exceeds 300 GHz, but the device breakdown voltage is low making it difficult to output high power signals
Solution Approach 1:
The invention segments the frequency and power functions across two different semiconductor technologies: the silicon-based die handles high-frequency signals (ft/fmax > 300 GHz) while the III-V semiconductor die handles high-power output (> 15 dBm). This segmentation allows each technology to operate in its optimal performance range.
Solution Approach 2:
The bumping pillars act as intermediaries that transmit high-frequency RF signals from the silicon-based die to the III-V semiconductor die for power amplification. This intermediary connection preserves the high-frequency characteristics while enabling high-power output through the III-V devices.
Data Source
AI summary
Various embodiments for die stacking are disclosed in the present disclosure for improved performance in RF circuit integration and packaging. In various layouts, a first die may be flipped and stacked on a second die via one or more bumping pillars coupled between the dies. The bumping pads may be disposed on the first die, the second die, or both. The bumping pads may comprise ground bumping pads for ground connection, RF signal bumping pads for cross-die RF signal transmission, and/or control bumping pads for biasing or logic control. Furthermore, the ground bumping pads and the RF signal bumping pad may form a ground-signal-ground pad structure for smooth RF signal transmission. The present embodiments may integrate a silicon-based die with an III-V semiconductor-based die together for a small form factor package with the well-defined ground to handle RF signals over millimeter-wave frequencies at high power levels.