Stacked RF Switch Parasitic Capacitance Management
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Solution Overview
Problem
In RF switching applications, increasing the number of FETs in a stack enhances voltage handling capacity but increases parasitic capacitance, which adversely affects tuning and impedance matching, requiring careful management of parasitic capacitance to maintain performance.
Innovation Solution
A radio frequency switch arrangement is implemented with a ground plane, a stack of switching elements, and a solder bump, where the stack is arranged relative to the ground plane, and the solder bump is positioned to overlap with the switching elements, with dimensions set to specific threshold values to manage parasitic capacitance contributions, thereby reducing total parasitic capacitance without significantly impacting resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the number of FETs in the stack is increased to enhance voltage handling capacity, then the voltage handling capability is improved, but the parasitic capacitance increases which adversely affects tuning and impedance matching
Solution Approach 1:
The patent extracts and removes the harmful parasitic capacitance effect by introducing a compensation capacitor that is coupled to subtract or cancel the parasitic capacitance generated by the FET stack. This allows the stack to maintain high voltage handling capability while the harmful capacitance effect is actively removed through the compensation mechanism.
Solution Approach 2:
The patent implements a feedback mechanism where the parasitic capacitance of the FET stack is measured or detected, and a compensation capacitor is adjusted or tuned to provide counteracting capacitance. This closed-loop approach allows the system to maintain optimal performance by continuously compensating for the parasitic effects as the stack configuration changes.
2Measurement precision
If the parasitic capacitance is reduced to improve tuning and impedance matching, then the tuning precision is improved, but the resistance in the on state increases
Solution Approach 1:
The patent extracts only the harmful parasitic capacitance component while preserving the functional capacitance needed for switching operation. By using a compensation capacitor that specifically targets and cancels the parasitic portion, the functional capacitance remains intact, maintaining low on-state resistance while improving tuning precision.
Solution Approach 2:
The patent changes the capacitance parameter dynamically by adjusting the compensation capacitor value to match and counteract the parasitic capacitance. This parameter adjustment allows the system to optimize tuning precision without permanently altering the fundamental capacitance that determines on-state resistance, thus maintaining both performance metrics.
Data Source
AI summary
Various implementations enable management of parasitic capacitance and voltage handling of stacked integrated electronic devices. Some implementations include a radio frequency switch arrangement having a ground plane, a stack and a first solder bump. The stack is arranged in relation to the ground plane, and includes switching elements coupled in series with one another, and a first end of the stack includes a respective terminal of a first one of the plurality of switching elements. The first solder bump is coupled to the respective terminal of the first one of the plurality of switching elements such that at least a portion of the first solder bump overlaps with one or more of the plurality of switching elements, an overlap dimension set in relation to a first threshold value in order to set a respective contribution to a parasitic capacitance of the radio frequency switch arrangement.