Stacked RF Switch Circuit for High-Voltage Attenuation Linearity
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Solution Overview
Problem
Modern high-speed wireless communication systems face challenges in designing RF transceivers with embedded Digital Step Attenuators (DSAs) that can tolerate overvoltage and undervoltage conditions without damage, due to the decreasing breakdown voltage of semiconductor technology nodes.
Innovation Solution
The proposed solution involves a switch circuit architecture that stacks transistors in series to enhance the maximum tolerable voltage, using cross-coupled p-type and n-type transistors with voltage clamps to maintain symmetry and linearity, and control circuitry to manage the conductive state of the transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If transistor gate oxide scaling is reduced to advance semiconductor technology nodes, then manufacturing precision and integration density are improved, but device breakdown voltage and overvoltage tolerance deteriorate
Solution Approach 1:
The patent divides a single high-voltage transistor into multiple lower-voltage transistors connected in series. Each transistor in the stack experiences only a portion of the total voltage, allowing the use of advanced technology nodes with thinner gate oxide while maintaining high voltage tolerance. For example, a 10V switch can be implemented using four 2.5V transistors stacked in series.
Solution Approach 2:
The patent transitions from a planar single-transistor architecture to a three-dimensional stacked architecture. By stacking transistors vertically in series, the voltage handling capability is extended in the vertical dimension while maintaining compatibility with advanced planar process technologies, enabling high voltage tolerance without requiring larger device footprints.
2Reliability
If transistors are stacked in series to increase voltage tolerance, then overvoltage tolerance is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple transistors into a unified stacked structure that functions as a single switch element. The series-connected transistors are controlled by a common control signal, and their combined behavior provides high voltage tolerance while presenting a simple two-terminal interface to the rest of the circuit, effectively hiding the internal complexity.
Solution Approach 2:
The stacked transistor structure serves multiple functions simultaneously: it provides high voltage tolerance, maintains low on-resistance, enables high-speed operation, and offers a simple control interface. This multi-functionality reduces the need for additional protective circuits or complex control logic, thereby offsetting the increased device complexity with functional integration.
3Power
If transistors are stacked in series to handle high voltage, then power handling capability is improved, but current consumption increases
Solution Approach 1:
The patent optimizes the electrical parameters of each transistor in the stack, including width, length, and gate voltage, to minimize the total on-resistance of the stacked structure. By carefully selecting and matching these parameters, the current consumption when the switch is on is kept low, offsetting the inherent increase from having multiple series devices.
Data Source
AI summary
A switch circuit is provided. The switch circuit includes a first node for coupling to a first conductive path and a second node for coupling to a second conductive path. Additionally, the switch circuit includes first and second stacks of transistors arranged between the first and second nodes. A first transistor of the first stack and a first transistor of the second stack are respectively cross-coupled with a second transistor of the second stack and a second transistor of the first stack. The first transistors of the first and the second stack are coupled to the first node. A third transistor of the first stack and a third transistor of the second stack are respectively cross-coupled with a fourth transistor of the second stack and a fourth transistor of the first stack. The fourth transistors of the first and the second stack are coupled to the second node.