Stacked RF Power Amplifier Interconnects Without Bond-Wire Inductance
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Solution Overview
Problem
Conventional RF power amplifier devices face challenges in high-frequency applications due to excessive inductance from bond wires, which can lead to manufacturing costs and device failure issues, and performance degradation from proximity to ground planes, necessitating the development of alternative interconnect methods.
Innovation Solution
The implementation of integrated interconnect structures, including conductive via structures and passive devices like IPDs, which provide impedance matching and harmonic termination without wire bonds, allowing for stacked topologies and reduced parasitic induction, thereby minimizing inductance and capacitive coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bond wires are used for interconnect, then electrical connection is achieved, but inductance increases and RF performance degrades
Solution Approach 1:
The patent removes bond wires from the interconnect structure entirely, replacing them with direct chip-to-substrate connections through conductive vias. This extraction eliminates the source of parasitic inductance while maintaining electrical connectivity between the RF amplifier die and external circuits.
Solution Approach 2:
The patent replaces the mechanical wire bonding process with a direct conductive via structure that integrates the interconnect function into the chip substrate itself. This substitution eliminates the mechanical bond wire interface and its associated inductance through a more integrated electrical connection method.
2Reliability
If bond wires are used for interconnect, then electrical connection is achieved, but manufacturing costs increase
Solution Approach 1:
The patent extracts and eliminates the bond wire component and bonding process from the manufacturing workflow. This removal reduces material costs (no longer needing gold or copper bond wires) and process costs (simplifying the assembly steps), while the conductive via structure is formed during standard chip fabrication.
Solution Approach 2:
The chip substrate itself provides the interconnect function through integrated conductive vias, eliminating the need for separate bond wire interconnection services. The chip structure serves its own interconnection needs, reducing dependency on additional components and assembly processes.
3Reliability
If bond wires are used for interconnect, then electrical connection is achieved, but assembly time increases
Solution Approach 1:
The patent removes the time-consuming wire bonding process from the assembly sequence. The conductive via connections are formed during chip fabrication, eliminating the need for post-fabrication wire bonding operations and reducing overall assembly time.
Solution Approach 2:
The interconnect structures (conductive vias) are formed in advance during chip fabrication before final assembly. This preliminary creation of connection paths eliminates the need for time-consuming post-assembly wire bonding operations.
4Reliability
If passive components are placed near ground plane, then impedance matching is achieved, but capacitive coupling increases and quality factor decreases
Solution Approach 1:
The patent utilizes the vertical dimension by routing connections through conductive vias that penetrate the substrate, allowing passive components to be positioned in three-dimensional space rather than constrained to a single plane. This vertical integration reduces parasitic capacitive coupling while maintaining impedance matching performance.
Data Source
AI summary
A radio frequency (RF) power amplifier device package includes a substrate and a first die attached to the substrate at a bottom surface of the first die. The first die includes top gate or drain contacts on a top surface of the first die opposite the bottom surface. At least one of the top gate or drain contacts is electrically connected to a respective bottom gate or drain contact on the bottom surface of the first die by a respective conductive via structure. An integrated interconnect structure, which is on the first die opposite the substrate, includes a first contact pad on the top gate contact or the top drain contact of the first die, and at least one second contact pad connected to a package lead, a contact of a second die, impedance matching circuitry, and/or harmonic termination circuitry.