Stacked RFIC-Antenna Package for Short Millimeter-Wave Interconnects
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Solution Overview
Problem
Existing semiconductor packaging technologies face challenges in achieving shorter interconnects between chips and antennas, particularly in millimeter-wave applications, due to conflicting requirements for substrate layers between antenna design and routing design, which limits package size and integration.
Innovation Solution
A semiconductor package structure comprising a bottom chip package with a semiconductor chip and a top antenna package, where the top antenna package includes a radiative dual-band or single-band antenna element mounted on a substrate with plated through-holes and conductive traces, allowing for separate optimization of chip and antenna substrates for efficient signal routing and reduced form factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If thin build-up layers are employed in substrate layers to enable thin vias and dense interconnects, then routing design requirements are met, but antenna design requirements are not met
Solution Approach 1:
The patent divides the package into two separate sub-packages: a bottom chip package containing the semiconductor chip and a top antenna package containing the antenna element. This segmentation allows each sub-package to be independently optimized - the bottom package can use thin build-up layers for dense routing while the top package can use thick substrate layers for antenna performance, thereby resolving the contradiction between routing and antenna design requirements
Solution Approach 2:
The patent transitions from a planar integration approach to a three-dimensional stacked package-on-package architecture. By moving the antenna to a separate vertical layer (another dimension), the design allows independent optimization of substrate thickness for routing (thin in bottom package) versus antenna (thick in top package) without spatial conflict, resolving the dimensional constraints of traditional single-plane integration
2Adaptability or versatility
If separate optimization of chip and antenna substrates is implemented, then design flexibility and integration are improved, but package complexity increases
Solution Approach 1:
The patent merges two separately optimized sub-packages (bottom chip package and top antenna package) into a single integrated package structure through mounting the top antenna package on the bottom chip package. This combining approach achieves the benefits of separate optimization (design flexibility, independent material selection) while presenting a unified integrated solution, thereby improving flexibility without proportionally increasing overall package complexity
3Length of moving object
If antenna element is integrated closer to the chip, then interconnect length is reduced, but substrate layer requirements conflict
Solution Approach 1:
By segmenting the package into bottom chip package and top antenna package with the antenna element disposed on the top side surface of the top antenna package, the patent achieves short interconnect length through vertical stacking while allowing the top antenna package to use thick substrate layers appropriate for antenna design, thus resolving the conflict between short interconnect requirements and substrate thickness requirements
Data Source
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AI summary
One embodiment of the present disclosure provides a semiconductor package including a bottom chip package (10) having a first side (10a) and a second side (10b) opposing the first side (10a), and a top antenna package (20) mounted on the first side (10a) of the bottom chip package (10). The bottom chip package (10) further includes a semiconductor chip (30). The semiconductor chip (30) may include a RFIC chip. The top antenna package (20) has at least one radiative antenna element (220).