Vertically Stacked Diode-Triggered SCR for Low-Distortion ESD Protection
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Solution Overview
Problem
Existing semiconductor structures, such as bulk string diodes, suffer from junction breakdown, poor voltage scaling, and harmonics distortion, especially in high-power applications, and often provide lower-than-desired electrostatic discharge (ESD) protection due to reliance on self-protection mechanisms.
Innovation Solution
A vertically stacked diode-trigger silicon controlled rectifier (SCR) is developed, featuring trigger diodes integrated with the SCR on a trap-rich semiconductor substrate, utilizing a polysilicon layer with P+ and N+ regions isolated by a gate dielectric, which eliminates the Darlington effect and provides low capacitance and harmonic distortion while being area-efficient, and fabricated using integrated circuit technologies like photolithographic processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bulk string diodes are used for ESD protection in RF-switches, then the device can provide basic current directionality, but it causes junction breakdown, poor voltage scaling, and harmonics distortion
Solution Approach 1:
The patent transitions from planar diode structures to vertically stacked three-dimensional structures. The diode-trigger SCR is built vertically with multiple layers (P+, N+, P, N regions) stacked along the vertical axis, allowing improved ESD protection and voltage handling without increasing lateral footprint. This vertical integration enables better current distribution and reduces junction breakdown risks.
Solution Approach 2:
The invention employs a composite structure combining diode and SCR elements in a single vertically integrated device. The structure includes P+ and N+ regions forming a diode trigger section, and P and N regions forming the SCR section, all integrated in a vertical stack. This composite architecture provides both diode rectification and SCR controlled switching functionality, improving ESD protection while reducing harmonics distortion through optimized carrier injection and recombination paths.
2Reliability
If vertically stacked diode-trigger SCR is implemented, then ESD protection level and area efficiency are improved, but device structure complexity increases
Solution Approach 1:
The patent merges diode trigger functionality and SCR controlled switching functionality into a single vertically integrated structure. The P+ and N+ regions form the diode trigger section, while the P and N regions form the SCR section, with shared intermediate regions. This merging reduces the number of separate components needed, simplifies the overall device architecture, and improves area efficiency while maintaining high ESD protection levels.
Solution Approach 2:
By stacking device layers vertically rather than arranging them laterally, the patent reduces the lateral footprint and improves area efficiency. The vertical integration of P+, N+, P, and N regions allows complex functionality to be achieved in a compact three-dimensional structure, managing device complexity through spatial optimization.
3Ease of manufacture
If conventional photolithographic processes are used for fabrication, then manufacturing compatibility is maintained, but additional masking steps are required
Solution Approach 1:
The patent designs the vertically stacked diode-trigger SCR to be fabricated using standard semiconductor manufacturing processes, including conventional photolithography and ion implantation. The structure utilizes universal process steps that can form multiple device regions (P+, N+, P, N regions) and doping profiles in a sequence of standard processing steps, maintaining compatibility with existing manufacturing infrastructure while achieving complex device functionality.
Data Source
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to vertically stacked diode-trigger silicon controlled rectifiers and methods of manufacture. The structure includes: a silicon controlled rectifier in a trap rich region of a semiconductor substrate; and at least one diode built in polysilicon (gate material) and isolated by a gate-dielectric.