Stacked Select Gate Structure for NAND Memory Cell String
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Solution Overview
Problem
Conventional NAND type flash memory devices face issues with non-uniform electric field bias conditions, leading to slower erase rates and reliability problems due to large spacing between select gates and wordlines, which complicates fabrication and results in fab-out Vt differences and challenges in using double patterning photolithography.
Innovation Solution
The implementation of a stacked select gate structure, where select gates are divided into multiple components with uniform spacing relative to core wordlines, ensuring consistent bias environments and facilitating double patterning photolithography, thereby achieving fab-out and erasure Vt uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large spacing is maintained between select gates and wordlines to suppress hot carrier injection, then reliability is improved, but erase rate decreases and fabrication complexity increases
Solution Approach 1:
The select gate is divided into multiple segments (first select gate component and second select gate component) separated by a first component. This segmentation allows the spacing between select gate components and wordlines to be reduced for faster erase rates, while the overall structure maintains sufficient spacing for hot carrier suppression. The segmented structure enables different regions to serve different functions optimally.
2Reliability
If large spacing is maintained between select gates and wordlines, then hot carrier injection is suppressed, but fab-out Vt uniformity deteriorates
Solution Approach 1:
Dividing the select gate into multiple components with controlled spacing creates a more uniform electric field distribution across all wordlines during erase operations. The segmented structure ensures that voltage is distributed more evenly, reducing Vt variations and improving manufacturing precision and device uniformity.
Solution Approach 2:
The stacked select gate structure with multiple components helps create more uniform potential distribution across the wordlines. By having multiple select gate components at different positions, the electric field is distributed more evenly during erase operations, reducing potential differences that cause Vt variations and improving equipotential conditions across the memory array.
3Reliability
If large spacing is maintained between select gates and wordlines, then hot carrier injection is suppressed, but double patterning photolithography becomes more difficult
Solution Approach 1:
The segmented select gate structure with multiple components and intervening dielectric layers creates a pattern that is more amenable to double patterning photolithography. The segmentation allows for staged fabrication processes where different components can be formed in separate steps, improving ease of manufacture while maintaining the spacing needed for hot carrier suppression.
Data Source
AI summary
A memory string is disclosed including a plurality of core cells serially connected between a source select gate and a drain select gate along a channel. Each core cell includes a wordline separated from the channel by a stack of layers including a charge trapping layer. At least one of the source and drain select gates is a stacked select gate with a plurality of components, including a first component adjacent to the plurality of core cells and a second component separated from the core cells by the first component. The first component includes a wordline separated from the channel by a stack of layers including a charge trapping layer, and a distance between the wordline of the first component and the wordline of a first core cell in the plurality of core cells is substantially the same as distances between each wordline in the plurality of word core cells.