Stacked Semiconductor Package Asymmetric Through Electrode Alignment
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Solution Overview
Problem
The design of stacked semiconductor packages faces challenges in optimizing the arrangement of through electrodes and function blocks on lower chips to accommodate upper chips effectively, limiting the flexibility and efficiency in stacking different types of semiconductor chips.
Innovation Solution
A stacked semiconductor package design where the lower chip features a through electrode area and a function block area, with the through electrode area disposed along a central axis in a transverse direction and the function block area separate from it, allowing for various orientations and alignments of the upper chip's pad area to correspond with the lower chip's through electrodes, enhancing compatibility and functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the through electrode area is disposed along the longitudinal direction of the lower chip to simplify alignment, then the alignment process is easier, but the function block area becomes limited and cannot be optimally arranged
Solution Approach 1:
The through electrode area is disposed along the transverse direction of the lower chip while the function block area is arranged along the longitudinal direction, creating an asymmetric layout that optimizes both alignment ease and function block arrangement flexibility. This asymmetric arrangement allows the upper chip's pad area to be aligned with the through electrodes while providing sufficient space for function blocks in the perpendicular direction.
2Stability of the object's composition
If the upper chip is strictly aligned with the lower chip's central axis to maintain structural symmetry, then the package structure is more regular, but the pad area and through electrode area cannot be optimally positioned
Solution Approach 1:
The invention intentionally introduces asymmetric positioning where the pad area of the upper chip is disposed along a central axis that is shifted from the central axis of the lower chip. This asymmetric arrangement enables optimal positioning of the pad area relative to the through electrode area while maintaining overall package stability through controlled offset distances.
Solution Approach 2:
The invention resolves the positioning conflict by introducing offset in the transverse direction while maintaining longitudinal alignment. This dimensional separation allows the pad area to be optimally positioned relative to the through electrodes without compromising the overall structural regularity of the stacked package.
3Reliability
If the through electrode area occupies a large area to ensure sufficient connection points, then the electrical connection is more reliable, but the function block area becomes insufficient
Solution Approach 1:
The lower chip is divided into distinct functional areas: a through electrode area disposed along the transverse direction and a function block area disposed along the longitudinal direction. This segmentation allows the through electrode area to provide sufficient connection points for reliable electrical connection while the function block area maintains adequate space for functional circuits, eliminating the trade-off between connection reliability and function block space.
Data Source
AI summary
Provided is a stacked semiconductor package which minimizes a limitation on a design of a lower semiconductor chip due to a characteristic of an upper semiconductor chip stacked on the lower chip. The stacked semiconductor package includes a lower chip having a through electrode area in which a plurality of through electrodes are disposed; and at least one upper chip stacked on the lower chip and having a pad area in which a plurality of pads corresponding to the plurality of through electrodes are disposed. The pad area is disposed along a central axis bisecting an active surface of the upper chip. The central axis where the pad area of the upper chip is disposed is placed at a position which is shifted from a central axis in a longitudinal direction of an active surface of the lower chip.