Stacked Semiconductor Device Back Gate Noise Isolation
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Solution Overview
Problem
Noise interference occurs between peripheral circuits and memory cells in semiconductor devices where a Si transistor is used for the peripheral circuit and an oxide semiconductor transistor is stacked above it, affecting data retention and power consumption.
Innovation Solution
Incorporating a metal oxide transistor with a channel formation region and using a conductive layer with a higher resistivity as a back gate to reduce noise influence, allowing for independent potential application to each region and optimizing threshold voltage and off-state current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If an oxide semiconductor transistor is stacked above a Si transistor peripheral circuit, then chip area is reduced and data retention is improved, but noise interference between circuits increases
Solution Approach 1:
An insulating layer is introduced between the oxide semiconductor transistor and the Si transistor peripheral circuit to act as a noise barrier. This intermediary layer blocks electrical noise from the peripheral circuit from interfering with the memory cell, while allowing the stacked configuration to maintain its area reduction benefits.
Solution Approach 2:
Different regions of the device are given different properties: the memory cell region uses oxide semiconductor transistors with high data retention, while the peripheral circuit region uses Si transistors for high-speed operation. The insulating layer provides localized noise isolation specifically where needed at the interface between these regions.
2Reliability
If an oxide semiconductor transistor is used in the memory cell, then off-state current is reduced and data retention is improved, but sensitivity to noise from peripheral circuits increases
Solution Approach 1:
The insulating layer serves as a protective intermediary that shields the oxide semiconductor transistor's sensitive channel region from noise generated by the peripheral circuit, allowing the transistor to maintain its low off-state current and high data retention characteristics without being adversely affected by electrical interference.
Solution Approach 2:
The insulating layer is positioned in advance to prevent noise interference before it can affect the oxide semiconductor transistor. This preliminary protective measure counteracts the inherent noise sensitivity of the oxide semiconductor material before noise can degrade data retention performance.
3Area of stationary object
If peripheral circuit and memory cell are in close proximity, then chip area is reduced, but noise interference and signal integrity deteriorate
Solution Approach 1:
The insulating layer acts as a spatial intermediary that enables close proximity placement of the peripheral circuit and memory cell while maintaining signal integrity. It provides electrical isolation that prevents noise coupling, allowing the design to achieve area reduction without sacrificing signal quality.
Data Source
AI summary
A novel storage device and a novel semiconductor device are provided.In the storage device, a cell array including a plurality of memory cells is stacked above a control circuit, and the cell array operates separately in a plurality of blocks. Furthermore, a plurality of electrodes are included between the control circuit and the cell array. The electrode is provided for a corresponding block to overlap with the block, and a potential of the electrode can be changed for each block. The electrode has a function of aback gate of a transistor included in the memory cell, and a potential of the electrode is changed for each block, whereby the electrical characteristics of the transistor included in the memory cell can be changed. Moreover, the electrode can reduce noise caused in the control circuit.