Stacked Semiconductor Byte-Order Alignment for Channel Skew
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Solution Overview
Problem
In stacked semiconductor devices, signal transmission skew occurs due to the mismatch between the mirror structure of base chip channel interfaces and the shift structure of core chip channels, affecting operation reliability.
Innovation Solution
The implementation of transfer control circuits that selectively swap channel commands and data words between pseudo-channels based on channel interface arrangements, ensuring synchronized data transfer between the base chip and core chips through through-electrodes, thereby aligning byte orders to minimize skew and enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If base chip channel interfaces use mirror structure and core chip channels use shift structure, then device integration and performance are improved, but signal transmission skew occurs affecting operation reliability
Solution Approach 1:
A transfer control circuit is introduced as an intermediary component between the base chip channel interfaces and core chip channels. This circuit receives data from the mirror-structured base chip interfaces, performs byte order conversion based on location information, and outputs to the shift-structured core chip channels, thereby mediating the structural mismatch and eliminating signal transmission skew
Solution Approach 2:
The transfer control circuit dynamically changes the byte order parameter of data based on location information signals. When receiving data from different channel interfaces (first-side or second-side), the circuit adjusts the byte sequence arrangement to match the corresponding channel structure, transforming the data representation to resolve the mirror-shift structure incompatibility
2Speed
If data words are transferred directly between base chip and core chips without byte order alignment, then data transfer speed is maintained, but signal transmission skew occurs
Solution Approach 1:
The transfer control circuit performs preliminary byte order conversion before data is output to the core chip channels. By pre-adjusting the byte sequence according to location information and channel structure requirements, the circuit ensures that data arrives at the destination in the correct format without requiring post-processing, thus maintaining transfer speed while ensuring reliability
Data Source
AI summary
A stacked semiconductor device includes at least one upper chip including first and second channels, each including first and second pseudo-channels; and first and second transfer control circuits respectively corresponding to the first and second channels, each configured to select one of the first and second pseudo-channels according to a channel designation signal designating one of the first and second pseudo-channels and a location information signal indicating a location of a corresponding channel, and transfer a data word between the selected pseudo-channel and a lower chip, wherein the first transfer control circuit transfers the data word in a first order in units of bytes, and the second transfer control circuit transfers the data word in a second order in units of bytes, opposite to the first order.