Stacked Semiconductor Capacitor Structure for High-Density Cells
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices integrate to higher densities, providing sufficient capacitance in a limited area becomes challenging, especially with the scaling down and miniaturization of MOS transistors, making it difficult for existing capacitors to supplement the required capacitance.
Innovation Solution
Incorporating a capacitor structure in the back end of line (BEOL) process with electrode structures connected by vias, and supplementing it with standard cells arranged below, forming a parallel connection to enhance capacitance, including a lower capacitor formed in the front end of line (FEOL) process to provide additional capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOS transistors are scaled down and miniaturized to increase integration density, then device integration density is improved, but capacitance is reduced
Solution Approach 1:
The patent transitions from planar capacitor structures to three-dimensional stacked capacitor structures with multiple electrode layers and vias. This vertical stacking in the third dimension increases capacitance without occupying additional lateral area, thereby maintaining high integration density while compensating for the capacitance reduction caused by transistor miniaturization.
Solution Approach 2:
The patent implements nested capacitor structures where multiple electrode layers are stacked vertically with dielectric layers in between, and vias connect corresponding electrodes across layers. This nested configuration packs multiple capacitive elements within a compact vertical space, increasing total capacitance while preserving lateral integration density.
2Quantity of substance
If capacitor size is increased to provide sufficient capacitance, then capacitance is improved, but device area is increased
Solution Approach 1:
The patent utilizes vertical stacking of multiple electrode layers and dielectric layers to increase capacitance in the vertical dimension rather than expanding laterally. This approach provides sufficient capacitance while maintaining a compact device footprint, effectively resolving the contradiction between capacitance and device area.
Solution Approach 2:
The patent employs composite capacitor structures combining multiple dielectric layers with different properties and multiple electrode materials, connected through vias. This composite approach achieves high capacitance density within a limited area by optimizing the electrical and physical properties of each layer in the stack.
Data Source
AI summary
A semiconductor device includes: a standard cell array including a plurality of standard cells, each of the plurality of standard cells; a plurality of power supply lines configured to provide a power supply voltage and extending in a first direction; a capacitor structure including electrode structures included in each of a plurality of dielectric layers formed on the standard cell array, the capacitor structure having vias connecting the electrode structures; and contacts electrically connecting the capacitor structure and the standard cell array to each other. Each of the plurality of standard cells provides a unit capacitor circuit having capacitance that is based on a connection structure of active regions and gates of first and second transistors thereof.