Stacked Semiconductor Package Center Pad Routing
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Solution Overview
Problem
As semiconductor technologies advance, the complexity of redistribution routing in stacked semiconductor devices increases, and the miniaturization trend leads to narrower line widths, making it challenging to implement simple and reliable redistribution routing.
Innovation Solution
A semiconductor package design featuring a pair of semiconductor chips with specific I/O pad arrangements and routing redistribution wires that connect terminals without intersecting the central line, allowing for direct electrical connections between chips and simplifying the redistribution routing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked semiconductor chips is increased to achieve high capacity, then the storage capacity or processing capability is improved, but the redistribution routing complexity increases significantly
Solution Approach 1:
The invention divides the redistribution routing function into two separate layers: the first semiconductor chip handles routing to the substrate, while the second semiconductor chip handles routing to semiconductor devices. This segmentation allows each chip to have simpler, dedicated routing paths rather than one chip handling all routing complexity, thereby enabling high capacity stacking without proportionally increasing routing complexity.
2Area of moving object
If the line width of redistribution routing is reduced to achieve miniaturization, then the device footprint is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The invention transitions the routing problem from a two-dimensional planar layout to a three-dimensional stacked architecture. By utilizing vertical stacking of semiconductor chips, the routing paths are distributed across multiple layers and dimensions, allowing for wider effective routing widths in the vertical dimension while maintaining small footprint in the horizontal plane, thereby reducing manufacturing precision requirements for line width control.
3Ease of operation
If the first semiconductor chip is electrically directly connected to the substrate, then the connection simplicity is improved, but the signal interference or crosstalk increases
Solution Approach 1:
The invention introduces the second semiconductor chip as an intermediary layer between the first semiconductor chip and the substrate. The second chip's terminals are electrically directly connected to the substrate, while the first chip connects to semiconductor devices through the second chip. This intermediary structure maintains connection simplicity through direct electrical paths while the layered architecture provides signal isolation that reduces interference and crosstalk.
Data Source
AI summary
A semiconductor package includes a substrate; and first and second semiconductor chips sequentially disposed on the substrate so that active surfaces of the first and second semiconductor chips face each other, wherein the first and second semiconductor chips are center pad-type semiconductor chips each having I/O pads arranged in two columns to be adjacent to a central line thereof, and I/O pads of the second semiconductor chip are electrically connected directly to the substrate without intersecting the central line of the second semiconductor chip.