3D Semiconductor Channel Structure for Carrier Mobility Gain
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Solution Overview
Problem
Conventional planar MOS transistors face challenges in scaling down, leading to the development of stereoscopic and non-planar transistor technologies like FinFET and gate-all-around nanowire FETs, but there is a need to further enhance electrical performance through structural design and process improvements.
Innovation Solution
A manufacturing method for semiconductor devices that incorporates a semiconductor channel structure with both horizontal and vertical portions, where the vertical portion is connected to horizontal portions, increasing the surface area and utilizing epitaxial materials to enhance carrier mobility and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional planar MOS transistor structure is used, then manufacturing process is simple, but device scaling is limited and electrical performance cannot be further improved
Solution Approach 1:
The patent transitions from conventional planar (2D) transistor structures to three-dimensional semiconductor channel structures with vertical portions extending upward from horizontal portions. This dimensional change increases the effective channel area and surface area covered by gate structures, thereby improving electrical performance including driving current and carrier mobility while maintaining manufacturing feasibility through epitaxial growth processes
2Productivity
If stereoscopic transistor structures like FinFET are adopted, then device miniaturization is achieved, but electrical performance enhancement is still limited
Solution Approach 1:
The semiconductor channel structure is divided into multiple horizontal portions stacked vertically, with vertical portions connecting them. This segmentation creates multiple independent channel regions that can be controlled by separate gate structures, increasing the total effective channel area and improving electrical performance beyond what single-structure FinFET designs can achieve
Solution Approach 2:
The patent employs composite material structures including semiconductor materials with different crystal orientations (e.g., <110> and <100> orientations) in different portions of the channel structure. This composite approach optimizes carrier mobility in vertical channels while maintaining structural integrity, achieving superior electrical performance compared to uniform material structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the electrical performance of semiconductor devices by increasing the surface area covered by the gate structure and improving carrier mobility, thereby improving driving current and other electrical characteristics.
Implementation Method 1
utilizing epitaxial materials to enhance carrier mobility and electrical performance
Data Source
AI summary
A manufacturing method of a semiconductor device includes the following steps. A first transistor is formed on a substrate. The first transistor includes a first semiconductor channel structure and two first source/drain structures. The first semiconductor channel structure includes first horizontal portions and a first vertical portion. The first horizontal portions are stacked in a vertical direction and separated from one another. Each of the first horizontal portions is elongated in a horizontal direction. The first vertical portion is elongated in the vertical direction and connected with the first horizontal portions. The two first source/drain structures are disposed at two opposite sides of each of the first horizontal portions in the horizontal direction respectively. The two first source/drain structures are connected with the first horizontal portions.