3D-Stacked Semiconductor Source/Drain Isolation With Channel Spacers
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Solution Overview
Problem
The formation of source/drain regions in 3D-stacked semiconductor devices is challenging due to difficulties in isolating upper and lower source/drain regions, particularly as contact poly pitch is scaled down, leading to overlapping issues and increased complexity in nanometer-scale areas.
Innovation Solution
The solution involves forming source/drain regions using channel spacers at the side surfaces of upper channel layers for the upper transistor, allowing for the formation of lower source/drain regions from lower channel layers while the channel spacer covers the upper channel layers. The channel spacer is then removed to expose the upper channel layers for the formation of upper source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If contact poly pitch is scaled down to achieve higher integration density, then device integration density is improved, but formation of lower and upper source/drain regions becomes more challenging due to overlapping issues
Solution Approach 1:
The patent segments the source/drain formation process into two distinct stages: first forming the lower source/drain region using lower channel layers as seed layers while protecting upper channel layers with channel spacers, then removing spacers and forming the upper source/drain region. This segmentation allows independent optimization of each region's formation, resolving the overlapping issue that arises from scaled-down pitch
Solution Approach 2:
The patent performs preliminary protection of upper channel layers by forming channel spacers before lower source/drain region formation. This preliminary action prevents contamination or unwanted epitaxial growth on upper channel layers during lower source/drain formation, enabling subsequent clean formation of upper source/drain regions after spacer removal
2Productivity
If lower source/drain region and upper source/drain region are formed in vertically overlapped positions, then device integration density is improved, but isolation of the two source/drain regions becomes difficult
Solution Approach 1:
The patent introduces channel spacers as intermediary protective structures during the lower source/drain formation process. These spacers act as a physical barrier that prevents interaction between lower source/drain formation materials and upper channel layers, ensuring proper isolation. After lower source/drain formation completes, spacers are removed to allow upper source/drain formation without contamination from lower regions
Solution Approach 2:
The formation process is segmented into sequential steps with clear isolation boundaries: Step 1 forms lower source/drain regions with upper channel layers protected by spacers, Step 2 removes spacers to expose upper channel layers, Step 3 forms upper source/drain regions. This segmentation ensures that lower and upper source/drain regions are formed in isolated conditions despite their vertical overlap, maintaining electrical isolation while achieving high integration density
Data Source
Figure 1
Figure 2A~2B
Figure 2C~2D
AI summary
Provided is a three-dimensional (3D) stacked semiconductor device which includes: a 1st source/drain region (135) connected to a 1st channel structure (112); and a 2nd source/drain region (145), above the 1st source/drain region (135), connected to a 2nd channel structure (122) above the 1st channel structure (112), wherein the 2nd channel structure (122) has a smaller length than the 1st channel structure (112) in a channel-length direction (D1), in which the 2nd source/drain region (145) is connected to a 3rd source/drain region through the 2nd channel structure (122).