Stacked Semiconductor Chip Interconnection via Vertical Metal Layers
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Solution Overview
Problem
The integration of multiple circuit elements, such as HBT and HEMT, on a single compound semiconductor chip leads to high process costs and low yield due to complex integration, resulting in large module size and significant signal loss and interference from long interconnections.
Innovation Solution
A semiconductor integrated circuit design featuring stacked chips with a compound semiconductor integrated circuit chip and an electronic circuit chip, utilizing a metal layer for electrical connections between chips, where Cu is used for interconnections and Au for contact with semiconductor devices to prevent performance degradation, allowing for shorter connections and more flexible layout design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple circuit elements (HBT and HEMT) are integrated on a single compound semiconductor chip, then circuit functionality is improved, but process cost increases and manufacturing yield decreases
Solution Approach 1:
The patent divides the integrated circuit into multiple separate chips: a compound semiconductor chip containing HBT circuit elements and a silicon chip containing HEMT circuit elements. These segmented chips are then interconnected through a substrate, achieving the desired circuit functionality while avoiding the high process costs and low yield associated with integrating both HBT and HEMT on a single compound semiconductor chip.
2Adaptability or versatility
If multiple circuit elements (HBT and HEMT) are integrated on a single compound semiconductor chip, then circuit functionality is improved, but manufacturing yield decreases
Solution Approach 1:
The patent divides the integrated circuit into multiple separate chips: a compound semiconductor chip containing HBT circuit elements and a silicon chip containing HEMT circuit elements. These segmented chips are then interconnected through a substrate, achieving the desired circuit functionality while avoiding the high process costs and low yield associated with integrating both HBT and HEMT on a single compound semiconductor chip.
3Ease of manufacture
If chips are placed in one plane, then electrical connections between chips are established, but module size increases and signal loss increases
Solution Approach 1:
The patent transitions from a planar two-dimensional arrangement of chips to a three-dimensional stacked configuration. Multiple chips are vertically stacked and interconnected through the substrate, enabling electrical connections while significantly reducing the horizontal footprint and overall module size. This vertical integration also shortens interconnection lengths, reducing signal loss.
4Ease of manufacture
If chips are placed in one plane, then electrical connections between chips are established, but signal loss and interference increase
Solution Approach 1:
The patent transitions from a planar two-dimensional arrangement of chips to a three-dimensional stacked configuration. Multiple chips are vertically stacked and interconnected through the substrate, enabling electrical connections while significantly reducing the horizontal footprint and overall module size. This vertical integration also shortens interconnection lengths, reducing signal loss.
5Device complexity
If circuit elements are integrated in one chip, then manufacturing process steps are reduced, but process cost increases
Solution Approach 1:
The patent divides the integrated circuit into multiple separate chips: a compound semiconductor chip containing HBT circuit elements and a silicon chip containing HEMT circuit elements. These segmented chips are then interconnected through a substrate, achieving the desired circuit functionality while avoiding the high process costs and low yield associated with integrating both HBT and HEMT on a single compound semiconductor chip.
Data Source
AI summary
The present invention relates to a compound semiconductor integrated circuit chip having a front and/or back surface metal layer used for electrical connection to an external circuit. The compound semiconductor integrated circuit chip (first chip) comprises a substrate, an electronic device layer, and a dielectric layer. A first metal layer is formed on the front side of the dielectric layer, and a third metal layer is formed on the back side of the substrate. The first and third metal layer are made essentially of Cu and used for the connection to other electronic circuits. A second chip may be mounted on the first chip with electrical connection made with the first or the third metal layer that extends over the electronic device in the first chip in the three-dimensional manner to make the electrical connection between the two chips having connection nodes away from each other.