Stacked Semiconductor Chip Structure with Overlapping Third Chip
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in achieving high integration and compactness while maintaining effective data processing performance, particularly in stacking multiple semiconductor chips to enhance storage capacity and reduce package size.
Innovation Solution
A semiconductor package design featuring a stacked structure with first and second semiconductor chips encapsulated in mold layers, where a third chip overlaps with the second chips to increase integration density and reduce package size, utilizing through mold vias for electrical connections and conductive trace patterns for interchip communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are stacked to increase storage capacity and integration density, then the storage capacity and integration density are improved, but the package size and structural complexity increase
Solution Approach 1:
The patent transitions from planar chip arrangement to three-dimensional stacked configuration, placing chips vertically at different height levels. Multiple chip stacks are arranged in the vertical dimension with overlapping horizontal projections, enabling high integration density while controlling package footprint through spatial utilization across multiple levels.
Solution Approach 2:
The patent implements nested arrangement where third chips are positioned within the horizontal projection area of second chip stacks, and fourth chips are positioned within the horizontal projection area of first chip stacks. This nesting approach allows chips to occupy overlapping horizontal spaces at different vertical levels, maximizing space utilization and reducing overall package size while maintaining high storage capacity.
2Quantity of substance
If multiple semiconductor chips are stacked to enhance integration density, then the integration density is improved, but the fabrication process complexity increases
Solution Approach 1:
The patent divides the semiconductor package into multiple independent chip stacks (first, second, third, fourth chips) that can be fabricated and prepared separately before final assembly. Each chip stack is encapsulated in its own mold layer, allowing modular fabrication processes that reduce overall process complexity compared to creating a monolithic multi-chip structure.
Solution Approach 2:
The patent introduces mold layers as intermediary encapsulation structures between chips and between chips and the package substrate. These mold layers facilitate the assembly process by providing a standardized interface and protective barrier, simplifying the integration of multiple chips while managing the complexity of interchip connections and positioning.
3Area of stationary object
If chips are arranged in stacked configuration to reduce package footprint, then the package size is reduced, but the electrical connection complexity increases
Solution Approach 1:
The patent extracts the electrical connection function from direct chip-to-chip contact and implements it through intermediary elements: pad structures on the package substrate and conductive connections within mold layers. This separation allows chips to be positioned in three-dimensional space with overlapping projections while electrical connections are established through dedicated pathways, managing connection complexity independently of physical arrangement.
Data Source
AI summary
A semiconductor package includes a plurality of stacked first semiconductor chips disposed over a substrate. At least a portion of the plurality of stacked first semiconductor chips is encapsulated in a first mold layer. The semiconductor package also includes a plurality of stacked second semiconductor chips disposed over the topmost chip of the stacked first semiconductor chips and the first mold layer. The semiconductor package also includes a third semiconductor chip disposed over the first mold layer and adjacent to the stacked second semiconductor chips. At least a portion of the third semiconductor chip overlaps with a portion of one or more of the stacked second semiconductor chips.