Stacked Semiconductor Chip Testing via Wafer-Level Probe Card
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Solution Overview
Problem
The manufacturing of stacked semiconductor memory requires a new test process to detect defects that can occur during both the wafer process and the stacking process, especially in System in Package (SiP) configurations, where unpackaged semiconductor chips need to be tested effectively.
Innovation Solution
A method involving the formation of a stacked structure with multiple semiconductor chips on a wafer, where a probe card is used to perform tests on the chips before and after the stacking process, ensuring that the positions of test pads on lower-layer chips match those on upper-layer chips, allowing for continuous testing with a wafer tester or probe card.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a new test process is introduced to detect defects in stacked semiconductor memory, then defect detection capability is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent performs wafer-level testing on lower-layer chips before the stacking process. This preliminary action identifies and isolates defective chips early, preventing them from being stacked with good chips. By testing in advance at the wafer level, the system improves defect detection capability while avoiding the need for complex post-stacking test equipment.
Solution Approach 2:
The testing process is segmented into two distinct stages: (1) wafer-level testing of lower-layer chips before stacking, and (2) chip-level testing of upper-layer chips after stacking. This segmentation allows each testing stage to use appropriate, simpler equipment rather than requiring a single complex system to handle all testing needs.
2Ease of manufacture
If unpackaged semiconductor chips are tested using conventional wafer testers, then testing cost is reduced, but testing effectiveness deteriorates due to inability to detect stacking defects
Solution Approach 1:
The patent performs preliminary testing of lower-layer chips at the wafer level before stacking occurs. This early detection capability identifies defects in the base chips that will support the stacked structure, ensuring only good chips are used as foundations. This approach maintains cost-effectiveness by using conventional wafer testers while improving overall testing effectiveness through multi-stage testing.
Solution Approach 2:
The testing process continues through multiple stages: wafer-level testing of lower layers, stacking, then chip-level testing of upper layers. This continuous testing approach ensures defects are detected at every stage of manufacturing, maintaining high testing effectiveness throughout the process while using cost-appropriate equipment for each stage.
3Measurement precision
If multiple testing stages are implemented for stacked semiconductor memory, then defect detection accuracy is improved, but manufacturing time increases
Solution Approach 1:
By performing wafer-level testing of lower-layer chips before stacking, the patent identifies and removes defective chips early in the process. This preliminary action prevents the need for time-consuming rework or identification of defects that would only be discovered after stacking is complete, thereby improving defect detection accuracy without proportionally increasing total manufacturing time.
Solution Approach 2:
The patent skips unnecessary intermediate testing steps by implementing a streamlined two-stage testing process. Rather than testing at every possible intermediate stage, the method focuses testing efforts at the most critical points: before stacking (wafer level) and after stacking (chip level). This selective approach maintains high defect detection accuracy while minimizing time loss.
Data Source
AI summary
Disclosed herein is a method for manufacturing a tested apparatus that includes forming a stacked structure that includes a plurality of first semiconductor chips stacked over a semiconductor wafer. The semiconductor wafer comprises a plurality of second semiconductor chips that are arranged in matrix of a plurality of rows and columns. Each of the first semiconductor chips is stacked over and electrically connected to a different one of the second semiconductor chips. The method further includes contacting a probe card to at least one of the first semiconductor chips to perform a first test operation on a corresponding one of the second semiconductor chips with an intervention of the at least one of the first semiconductor chips so that a plurality of tested apparatus each comprising a pair of first and second semiconductor chips stacked with each other is derived.