Stacked Semiconductor Chip Yield via Segmentation
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Solution Overview
Problem
The manufacturing yield of semiconductor devices with stacked semiconductor chips is hindered by the increasing probability of structural defects in larger chips, leading to decreased yield and increased costs.
Innovation Solution
A semiconductor device design featuring two or more stacked bodies with multiple semiconductor chips, each comprising bonded semiconductor layers, connected to logic chips via interconnects and sealed with resin, allowing for independent electrical connections and reduced chip size to enhance yield and memory capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of each semiconductor chip is increased to enlarge circuit scale and memory capacity, then the memory capacity is improved, but the probability of structural defects increases and manufacturing yield decreases
Solution Approach 1:
The patent divides a single large-capacity memory device into multiple smaller semiconductor chips stacked vertically. Each chip has reduced size with lower defect probability, but collectively they provide the required total memory capacity through the stacked configuration, thus resolving the contradiction between capacity and yield.
Solution Approach 2:
The patent transitions from a two-dimensional planar layout to a three-dimensional stacked structure. By arranging multiple chips in the vertical dimension rather than expanding horizontally, the system achieves increased memory capacity while maintaining smaller individual chip sizes, thereby improving manufacturing yield.
2Device complexity
If the size of each semiconductor chip is increased to enlarge circuit scale, then the circuit scale is improved, but the probability of structural defects increases and manufacturing yield decreases
Solution Approach 1:
The patent segments the circuit functionality across multiple smaller chips rather than implementing it in a single large chip. Each chip contains a portion of the total circuit scale, reducing the complexity and defect risk of individual devices while achieving the required overall circuit scale through the stacked assembly.
3Quantity of substance
If multiple semiconductor chips are stacked to increase memory capacity, then the memory capacity is improved, but the manufacturing cost increases due to decreased yield
Solution Approach 1:
By segmenting the memory device into multiple smaller chips, the patent improves manufacturing yield since smaller chips have lower defect probabilities. Although more chips are needed to achieve the same total capacity, the increased yield offsets the additional stacking complexity, ultimately reducing manufacturing cost.
Data Source
AI summary
A semiconductor device includes a base member having a first surface and a second surface on a side opposite to the first surface, the base member including at least one interconnect extending in a first direction along the first surface; two or more stacked bodies arranged in the first direction on the first surface, each of the two or more stacked bodies including semiconductor chips stacked in a second direction perpendicular to the first surface; and logic chips electrically connected respectively to the stacked bodies. Each of semiconductor chips includes first and second semiconductor layers. The first and second semiconductor layers each have an element surface and a back surface. An active element is provided on the element surface. The first semiconductor layer and the second semiconductor layer are bonded such that the element surface of the second semiconductor layer faces the element surface of the first semiconductor layer.