Stacked Semiconductor Chips with Hybrid Bonding for Memory Cell Density
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Solution Overview
Problem
The semiconductor industry faces challenges in maximizing chip area utilization as feature sizes shrink, requiring innovative designs to enhance memory cell density and flexibility in storage node design.
Innovation Solution
A semiconductor structure where chips are stacked on a substrate with transistors and storage nodes on opposite sides, electrically connected using a hybrid bonding method, allowing for flexible placement of memory cells and routing structures across chips to reduce footprint and improve area utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If chips are stacked with transistors and storage nodes on the same chip, then the device complexity is reduced, but the chip area utilization is insufficient
Solution Approach 1:
The memory cell components are segmented across two separate chips: the first chip contains the transistor while the second chip contains the storage node. This segmentation allows each chip to be optimized independently for its specific function, improving overall chip area utilization while maintaining the simplicity of each individual chip design.
Solution Approach 2:
The invention transitions from a planar single-chip architecture to a three-dimensional stacked architecture. By stacking the second chip containing the storage node above the first chip containing the transistor, the design utilizes the vertical dimension to improve chip area utilization without increasing the footprint of individual chips.
2Ease of manufacture
If transistors and storage nodes are integrated on the same chip, then the manufacturing process is simpler, but the memory cell footprint is larger
Solution Approach 1:
The memory cell is segmented into two separate chips, with the transistor on the first chip and the storage node on the second chip. This segmentation reduces the memory cell footprint by distributing components vertically, while the standardized chip interfaces maintain manufacturing simplicity through established bonding processes.
Solution Approach 2:
The second chip containing the storage node is effectively nested above the first chip containing the transistor, creating a compact vertical structure. This nesting approach reduces the horizontal footprint of the memory cell while maintaining manufacturability through standard chip stacking techniques.
3Reliability
If chips are bonded using hybrid bonding method, then the electrical performance is improved, but the manufacturing complexity increases
Solution Approach 1:
The hybrid bonding approach merges copper-to-copper bonding with dielectric-to-dielectric bonding in a single process. This combination achieves superior electrical performance through direct copper interconnection while the simultaneous dielectric bonding simplifies the overall manufacturing process by reducing the number of separate steps required.
Data Source
AI summary
A semiconductor structure, including a substrate and multiple chips, is provided. The chips are stacked on the substrate. Each of the chips has a first side and a second side opposite to each other. Each of the chips includes a transistor adjacent to the first side and a storage node adjacent to the second side. Two adjacent chips are bonded to each other. The transistor of one of the two adjacent chips is electrically connected to the storage node of the other one of the two adjacent chips to form a memory cell.