Stacked Semiconductor Chips With Vertical Inductors
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Solution Overview
Problem
The downscaling of memory devices with wireless communication functionality is hindered due to the dependence of communication performance on the area of inductor elements, which limits the integration of wireless communication with memory in IoT applications.
Innovation Solution
A semiconductor device configuration that stacks semiconductor chips with inductor portions on insulation films, allowing for flexible layout and increased area for inductor elements without affecting the memory cell area, using TSVs and bumps to electrically connect inductor portions across chips, thereby enhancing antenna performance and reducing signal loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If inductor elements are integrated with memory cells in the same chip, then device area is reduced, but communication performance deteriorates due to limited inductor area
Solution Approach 1:
The patent divides the device into separate functional modules: memory cells are integrated on one chip while inductor elements are formed on another chip, which is then stacked on top of the memory chip. This segmentation allows each component to be optimized independently for its specific function while maintaining compact overall device area.
Solution Approach 2:
The patent transitions from planar integration to three-dimensional stacking by forming the inductor elements on a separate chip that is vertically stacked on the memory chip. This dimensional change enables the inductor area to be increased without consuming additional planar area, thereby improving communication performance while maintaining compact device footprint.
2Reliability
If inductor area is increased to improve communication performance, then device area increases, preventing downscaling
Solution Approach 1:
The patent utilizes vertical stacking to increase inductor area by adding a third dimension. The inductor elements are formed on a separate chip that is stacked vertically on the memory chip, allowing the inductor area to be increased without expanding the planar footprint of the device, thus enabling downscaling while maintaining communication performance.
Solution Approach 2:
The separate chip structure serves multiple functions: it provides a dedicated platform for forming large-area inductor elements while also serving as an interconnection layer between the memory cells and external wireless communication antennas. This multi-functionality allows the device to maintain compact size while achieving both high communication performance and downscaling.
3Quantity of substance
If memory cell area is increased to store more information, then device area increases, but inductor area for wireless communication is limited
Solution Approach 1:
The patent segments the device functionality by placing memory cells on one chip and inductor elements on a separately stacked chip. This allows the memory cell area to be maximized for storage capacity while the inductor area on the stacked chip can be independently optimized for wireless communication, eliminating the area trade-off between storage and communication functions.
Solution Approach 2:
By stacking the inductor-containing chip vertically on the memory chip, the patent enables the inductor area to be increased in the vertical dimension without consuming additional planar area that would be needed for memory expansion. This allows both large storage capacity and adequate inductor area for wireless communication to coexist in a compact device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables efficient wireless communication while allowing for downscaling of semiconductor devices by separating inductor elements from memory cells, improving antenna performance and reducing signal loss through increased inductor area without increasing memory cell area.
Implementation Method 1
A first inductor portion 330a is provided on a first surface F1 or a second surface F2 of the semiconductor chip 30a. A second inductor portion 330b is provided on a third surface F3 or a fourth surface F4 of the semiconductor chip 30b
Data Source
AI summary
A semiconductor device includes a first and a second chips. A first inductor is above a first surface or a second surface located on an opposite side to the first surface. A first metal electrode is between the first and second surface to penetrate through the first substrate and to be connected to the first inductor. The second chip includes a second element provided on a third surface of a second substrate. A second inductor provided above a third surface of the second substrate or a fourth surface located on an opposite side to the third surface. A second metal electrode is provided between the third surface and the fourth surface to penetrate through the second substrate and to be connected to the second inductor. The first and second chips are stacked. The first and second inductors are electrically connected via the first or second metal electrode, as one inductor.