Stacked Semiconductor Chips With Vertical Interconnectors
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Solution Overview
Problem
The challenge lies in stacking semiconductor chips while exposing all chip pads, especially when chips have pads at both edges, due to limitations in existing integration technologies, which hinder the formation of high-performance and high-capacity semiconductor packages with small thickness.
Innovation Solution
The solution involves stacking semiconductor chips vertically with offset-stacking and using redistribution layers connected to one-side chip pads, forming vertical interconnectors that extend in the vertical direction, and a molding layer with landing pads to ensure electrical connectivity through a package redistribution layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are stacked vertically to increase integration, then the degree of integration is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent segments the chip stacking process into distinct stages: forming recesses in the molding compound, placing chips in specific orientations, and selectively exposing pads. This segmentation allows complex multi-chip stacking to be managed through systematic, repeatable steps, resolving the contradiction between high integration and manufacturing complexity
Solution Approach 2:
The patent transitions from planar chip arrangement to three-dimensional vertical stacking, enabling multiple chips to be integrated in the vertical dimension. This dimensional change dramatically increases integration density while the standardized stacking process manages the associated manufacturing complexity
2Reliability
If all chip pads are exposed for connectivity, then the electrical connectivity is improved, but the package thickness increases
Solution Approach 1:
The patent employs asymmetric chip stacking where chips are positioned with different orientations and offset arrangements. This asymmetry allows certain pads to be exposed on the package surface while other pads remain connected through vertical interconnectors, achieving full electrical connectivity without requiring all pads to be exposed, thus maintaining thin package profile
Solution Approach 2:
The patent introduces vertical interconnectors as intermediary elements that provide electrical connection between pads on different chip layers. These interconnectors enable pads that are not exposed on the surface to still achieve electrical connectivity, resolving the contradiction between pad exposure and package thickness
3Ease of operation
If offset-stacking is used to expose pads, then the pad exposure is improved, but the structural complexity increases
Solution Approach 1:
The patent performs preliminary actions by pre-forming recesses in the molding compound at precise locations before chip placement. This preliminary structuring guides the offset-stacking process, making pad exposure straightforward while managing structural complexity through advance planning and standardized recess patterns
Data Source
AI summary
A semiconductor package may include: a chip stack including a plurality of semiconductor chips stacked in a vertical direction; vertical interconnectors, each having first ends that are connected to the plurality of semiconductor chips, respectively, and extending in the vertical direction; a molding layer covering the chip stack and the vertical interconnectors while exposing second ends of the vertical interconnectors; landing pads formed over one surface of the molding layer to be in contact with the second ends of the vertical interconnectors, respectively, wherein the landing pads are conductive and overlap the first ends of the vertical interconnectors, respectively; and a package redistribution layer electrically connected to the vertical interconnectors through the landing pads.