Stacked Semiconductor Interconnect Layout for Common TSV Masks
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Solution Overview
Problem
The fabrication of stacked semiconductor devices with heterogeneous chips requires redesigning photomask sets for through substrate vias (TSVs) due to varying positions of metal terminals on logic chips, leading to inefficiencies and increased costs.
Innovation Solution
A method of fabricating stacked semiconductor devices using common photomask sets for through vias and internal wire layers, combined with redistribution lines and conductive pins, allowing for flexible connection of memory and logic chips without the need for custom photomask sets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the positions of TSVs are changed according to each logic chip design to enable flexible connection, then the adaptability to different logic chips is improved, but the photomask sets must be redesigned for each logic chip, increasing device complexity and manufacturing cost
Solution Approach 1:
The patent segments the TSV positions into two types: first type TSVs at fixed positions for standard memory chip fabrication, and second type TSVs at variable positions that can be selectively formed or left empty. This segmentation allows the memory chip to adapt to different logic chip configurations without requiring complete photomask redesign, as only the second type TSV positions need to be adjusted.
Solution Approach 2:
The patent creates a universal memory chip design with standardized first type TSV positions that can work with multiple different logic chip designs. The second type TSV positions provide flexibility to accommodate various logic chip terminal arrangements, making the memory chip universally compatible while maintaining manufacturing efficiency through common photomask sets for the first type TSVs.
2Productivity
If common photomask sets are used for fabricating memory chips, then the manufacturing efficiency and cost are improved, but the connection flexibility to different logic chip terminal positions deteriorates
Solution Approach 1:
The patent divides TSV positions into first type (fixed, formed with common photomask sets) and second type (variable, selectively formed). This segmentation enables manufacturing efficiency through standardized photomask sets for the majority of TSVs, while retaining connection flexibility through the selectively formed second type TSVs that can be adapted to different logic chip terminal positions.
Solution Approach 2:
The patent introduces dynamic flexibility by allowing the second type TSV positions to be selectively formed or left empty based on the specific logic chip being paired. This dynamic approach maintains high manufacturing efficiency through common photomask sets while providing the adaptability to connect to different logic chip terminal arrangements as needed.
3Ease of manufacture
If TSV positions are fixed for standard memory chip fabrication, then the manufacturing process simplicity is improved, but the ability to connect to varying logic chip terminal positions deteriorates
Solution Approach 1:
The patent segments TSV positions into first type (fixed for manufacturing simplicity) and second type (variable for connection adaptability). The first type TSVs are formed at standardized positions using common photomask sets, maintaining fabrication simplicity, while the second type TSVs provide the necessary flexibility to connect to varying logic chip terminal positions.
Solution Approach 2:
The patent performs preliminary action by pre-forming the first type TSVs at fixed positions during standard memory chip fabrication using common photomask sets. The second type TSVs are then selectively formed or left empty based on the specific connection requirements, allowing the memory chip to be pre-prepared for manufacturing efficiency while retaining adaptability for different logic chip pairings.
Data Source
AI summary
A stacked semiconductor device includes first chips and a second chip. The first chips are arranged in an array, and includes first and second type through vias, an internal wire layer, a redistribution line and conductive pins. The internal wire layer is disposed on and electrically connected to the first and second type through vias. The redistribution line is disposed on and electrically connected to the second type through vias and the internal wire layer, wherein the redistribution line extends from a top surface of the second type through vias to a position non-overlapped with the second type through vias. The conductive pins are disposed on and electrically connected to the redistribution line. The second chip is stacked on the first chips, wherein the second chip includes connection pins, and the second chip is connected to the first chips by bonding the connection pins to the conductive pins.