Stacked Semiconductor Substrates for Compact Multi-Chip Layout
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Solution Overview
Problem
Conventional semiconductor devices with multiple semiconductor elements mounted on a single substrate face challenges in minimizing the device's planar size due to the spatial arrangement of the elements, which limits design flexibility and increases the distance between elements, affecting electrical characteristics.
Innovation Solution
The semiconductor device incorporates a first and second substrate, with semiconductor elements mounted on both substrates in a manner that the third semiconductor element overlaps the second in plan view, allowing for a more compact design and reduced wiring length between elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If semiconductor elements are arranged next to one another on a single substrate, then the device structure is simple, but the planar size is enlarged
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of semiconductor elements to a three-dimensional stacked configuration using multiple substrates arranged in the vertical direction. This dimensional change allows elements to be positioned on different substrates at different heights, reducing the required planar area while maintaining functional connectivity through vertical wiring structures.
Solution Approach 2:
The patent divides the semiconductor device into multiple independent substrates (first substrate, second substrate, third substrate) that are stacked vertically. Each substrate can independently carry semiconductor elements, allowing the overall device to achieve compact planar dimensions by distributing elements across multiple segmented layers rather than concentrating them on a single large substrate.
2Ease of manufacture
If semiconductor elements are arranged next to one another on a single substrate, then the manufacturing process is simple, but the distance between elements is increased
Solution Approach 1:
By stacking substrates in the vertical direction, the patent reduces the horizontal distance between semiconductor elements that are positioned on adjacent substrates. Elements on the first substrate can be directly connected to elements on the second substrate through vertical wiring, significantly shortening inter-element distances compared to lateral arrangements on a single substrate.
Solution Approach 2:
The patent implements a nested substrate structure where multiple substrates are stacked and interconnected, with each substrate containing semiconductor elements. This nested configuration allows elements on different substrates to be in close proximity vertically, reducing the distance between elements while maintaining modular manufacturability through standardized substrate processing.
3Device complexity
If multiple semiconductor elements are mounted on a single substrate, then the device structure is simple, but the design flexibility is limited
Solution Approach 1:
The patent segments the device into multiple independent substrates, each of which can be independently designed, optimized, and manufactured. This segmentation allows different substrates to have different thicknesses, wiring layouts, and element configurations, providing significant design flexibility while maintaining a relatively simple overall stacked structure.
Solution Approach 2:
By utilizing the vertical dimension through stacked substrates, the patent enables independent optimization of each substrate's design parameters (thickness, wiring layout, element placement) without constraining the other substrates. This vertical stacking approach provides design freedom in both the lateral and vertical dimensions, allowing customized configurations for each functional layer.
Data Source
AI summary
A semiconductor device includes a first substrate, a second substrate spaced apart from the first substrate, a first semiconductor element mounted on an upper surface of the first substrate and an upper surface of the second substrate so as to extend across the first substrate and the second substrate, a second semiconductor element mounted on the upper surface of the second substrate, and a third semiconductor element mounted on a lower surface of the second substrate. The third semiconductor element overlaps the second semiconductor element in plan view.