Stacked Semiconductor Package With Concave Substrate And Vertical Interconnects
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Solution Overview
Problem
Current stacked layer type semiconductor packages with multiple pins face challenges in compactness, thickness, and reliability due to increased connection terminals, thermal expansion coefficient differences between semiconductor chips and resin interposers, leading to bulkiness and potential package failures.
Innovation Solution
A semiconductor package design featuring a semiconductor chip mounted on a substrate with a concave portion and a wiring line structure allowing external connection just above and under the chip, using a silicon or alternative substrate with matched thermal expansion coefficients to minimize thermal issues and enable compact, slim packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If packages with multiple pins are stacked with each other, then connection performance is improved, but package area and thickness increase
Solution Approach 1:
The patent transitions from planar connection terminals to three-dimensional vertical connections by positioning connection terminals on both the upper and lower surfaces of the semiconductor chip. This allows electrical connections to be established in multiple spatial dimensions, enabling compact stacked configurations without increasing package footprint area.
Solution Approach 2:
The patent implements nested packaging by placing one semiconductor chip vertically above another with their connection terminals facing each other. The upper chip is positioned within the vertical space above the lower chip, creating a compact stacked structure where multiple functional units are nested in the vertical dimension rather than occupying horizontal space.
2Reliability
If connection terminals are increased for high performance, then electrical connectivity is improved, but package compactness deteriorates
Solution Approach 1:
The patent utilizes vertical stacking to organize multiple connection terminals in the z-dimension rather than spreading them out in the x-y plane. Connection terminals are arranged on both upper and lower chip surfaces, allowing high-density interconnects to be achieved through vertical layering instead of horizontal expansion.
3Productivity
If semiconductor chips with multiple pins are used, then processing capability is improved, but thermal expansion differences cause wire disconnections
Solution Approach 1:
The patent changes the material parameter of the substrate from conventional resin to silicon, which has a thermal expansion coefficient matching that of semiconductor chips. This parameter change eliminates thermal expansion mismatch during temperature cycling, preventing wire bond disconnections while maintaining support for high-performance multiple-pin chips.
4Ease of manufacture
If resin interposers are used, then manufacturing ease is improved, but thermal expansion mismatch reduces reliability
Solution Approach 1:
The patent changes the substrate material from resin to silicon, fundamentally altering the thermal expansion parameter to match semiconductor chips. This material substitution resolves the thermal mismatch problem while silicon substrate technology remains well-established in semiconductor manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves a compact and slim semiconductor package with improved reliability, capable of handling high-performance multiple-pin chips, reducing the risk of thermal-related failures and enhancing manufacturing yield in stacked configurations.
Implementation Method 1
there is a large difference in thermal expansion coefficients between the silicon and interposers... due to differences in the thermal expansion coefficients between the semiconductor chips and the interposers
Data Source
AI summary
In a stacked layer type semiconductor package constructed by stacking a plurality of packages with each other, the plurality of packages include a semiconductor package including: a semiconductor chip; a substrate in which a concave portion has been formed, the semiconductor chip being mounted in the concave portion; and a wiring line structure constructed in such a manner that the wiring line structure can be externally connected to the semiconductor chip at least just above and just under the semiconductor chip.