Stacked Semiconductor Device Contact Plug Extension Layer
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Solution Overview
Problem
The challenge in fabricating stacked semiconductor devices is forming stable connections between transistors due to high electrical resistance caused by thin body patterns and the difficulty in creating good contacts through interlevel insulation films, particularly when using silicide to connect transistors.
Innovation Solution
The solution involves forming a contact plug between the drain or source region of the lower transistor and the source or drain region of the upper transistor, with an extension layer on the lateral face of the upper transistor's source or drain region to enlarge the contact area, and converting spacers into silicide layers to reduce contact resistance, thereby stabilizing the connection between stacked transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicide is used to connect the body pattern to a contact plug, then electrical connection is established, but electrical resistance becomes very high due to the thin body pattern
Solution Approach 1:
The invention transitions from a single-plane contact approach to a three-dimensional contact structure. The contact plug extends vertically through the interlevel insulation film to reach the body pattern, creating a vertical connection path. Additionally, the source/drain regions are extended laterally to increase the contact footprint, effectively adding both vertical and lateral dimensions to the contact interface, thereby reducing electrical resistance.
Solution Approach 2:
The invention performs preliminary extension of the source and drain regions before forming the contact plug. By pre-extending these regions to create larger contact surfaces, the subsequent contact formation process achieves lower resistance without requiring additional complex steps. This preliminary preparation ensures that when the contact plug is formed, it immediately establishes a low-resistance connection.
2Productivity
If the body pattern is made thin to increase transistor density, then device density increases, but contact formation becomes difficult and connection stability decreases
Solution Approach 1:
The invention compensates for the thin body pattern by extending the contact plug vertically through the insulation layers and extending the source/drain regions laterally. This multi-dimensional contact approach maintains high transistor density while ensuring stable electrical connection, as the connection stability depends on the extended vertical and lateral contact paths rather than the thin body pattern thickness.
Solution Approach 2:
The extended source and drain regions act as intermediary structures between the thin body pattern and the contact plug. These extended regions provide a larger surface area for electrical connection, mediating the connection between the thin body pattern (which cannot be thickened without reducing density) and the contact plug, thereby ensuring stable connection while maintaining high density.
3Object-affected harmful factors
If contact area is increased to reduce resistance, then electrical resistance decreases, but device area increases
Solution Approach 1:
The invention reduces resistance by increasing contact area in the vertical dimension through the contact plug extending through insulation layers, and in the lateral dimension through extended source/drain regions. This multi-dimensional area increase achieves lower resistance without proportionally increasing the planar footprint, as the vertical extension occurs beneath the surface rather than expanding the device's horizontal dimensions.
Solution Approach 2:
The contact plug is nested within the interlevel insulation film structure, extending vertically through the insulation layers to reach the body pattern. This nested configuration allows the contact plug to provide additional contact area without occupying extra lateral space, as it is embedded within the existing insulation film volume rather than expanding the device's external dimensions.
Data Source
AI summary
A stacked semiconductor device comprises a lower transistor formed on a semiconductor substrate, a lower interlevel insulation film formed on the semiconductor substrate over the lower transistor, an upper transistor formed on the lower interlayer insulation film over the lower transistor, and an upper interlevel insulation film formed on the lower interlevel insulation film over the upper transistor. The stacked semiconductor device further comprises a contact plug connected between a drain or source region of the lower transistor and a source or drain region of the upper transistor, and an extension layer connected to a lateral face of the source or drain region of the upper transistor to enlarge an area of contact between the source or drain region of the upper transistor and a side of the contact plug.