Stacked Semiconductor Converter Noise Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The complexity of semiconductor manufacturing processes increases due to the need for a two-layer wiring structure in stacked semiconductor chips, which complicates noise reduction between chips during flip-chip bonding.
Innovation Solution
A semiconductor apparatus design where the second semiconductor chip is stacked on the first chip such that the converter area does not overlap the first chip, reducing noise interference and simplifying the manufacturing process by positioning the converter area closer to the edge of the second chip, thereby avoiding noise from the wiring and ground layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a two-layer wiring structure is used between stacked semiconductor chips to reduce noise, then noise reduction is improved, but device complexity increases
Solution Approach 1:
The patent extracts the converter circuit from the overlapping region between stacked chips and places it in a non-overlapping area. This separation removes the converter from the noise-prone environment created by the two-layer wiring structure, reducing noise interference without requiring the complex two-layer wiring configuration throughout the entire device.
Solution Approach 2:
The patent introduces a ground layer as an intermediary between the converter circuit and the wiring layers. This ground layer acts as a shield that isolates the converter from electromagnetic noise generated by the wiring, providing noise reduction without requiring the converter to be positioned under complex multi-layer wiring structures.
2Device complexity
If converters are placed in overlapping areas between stacked chips, then device integration is improved, but noise interference increases
Solution Approach 1:
The patent segments the chip structure into overlapping and non-overlapping regions, and strategically places the converter circuit in the non-overlapping region. This segmentation allows the device to maintain integrated chip stacking in the overlapping areas while protecting the noise-sensitive converter by locating it in the noise-free non-overlapping area.
Solution Approach 2:
The patent applies different functional qualities to different regions of the device. The overlapping regions are optimized for signal transmission and chip stacking, while the non-overlapping region is designated as a noise-free zone for housing the converter circuit. This local differentiation ensures that each region serves its optimal function without compromising the other.
3Productivity
If wiring layers and ground terminals are positioned close to converters, then connection efficiency is improved, but crosstalk noise increases
Solution Approach 1:
The patent positions a ground layer as an intermediary between the wiring layers and the converter circuit. This ground layer acts as a electromagnetic shield that blocks crosstalk noise from the wiring while still allowing efficient signal connections to the converter, thus maintaining connection efficiency while reducing noise interference.
Data Source
AI summary
According to one embodiment, a semiconductor apparatus includes a substrate, a first semiconductor chip, a second semiconductor chip and a first converter. The first semiconductor chip includes a first surface and a second surface and is mounted on the substrate, the first surface is opposed to the substrate, the second surface is opposed to the first surface. The second semiconductor chip includes a first area and is stacked on the second surface. The first converter is arranged in the first area, the first converter is configured to perform at least one of analog-to-digital conversion and digital-to-analog conversion and arranged in the first area. A part of the first area does not overlap the first semiconductor chip when viewed from a direction perpendicular to the second surface.