3D Stacked Semiconductor Bonding Structure for Cut Defect Reduction
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Solution Overview
Problem
The challenge in the electronics market is the demand for miniaturization and weight reduction of electronic components, which requires improved integration of semiconductor devices while minimizing defects during the cutting process.
Innovation Solution
A semiconductor device design featuring a first chip structure with a substrate, circuit elements, and a second chip structure with memory cells, bonded via metal and insulating layers, and a protective insulating layer extending to the edge region, along with a method of manufacturing that includes partial separation of substrate structures and bonding at the wafer level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If miniaturization and weight reduction are pursued, then integration degree is improved, but defects during cutting process increase
Solution Approach 1:
The substrate structure is divided into a first substrate and a second substrate that are bonded together. The second substrate is further divided into multiple chip regions. This segmentation allows the device to be miniaturized while maintaining structural integrity during cutting, as each segment can be processed independently with reduced stress concentration.
Solution Approach 2:
Bonding metal layers and insulating layers are formed on the first substrate before the cutting process. The protective insulating layer is formed to extend over edge regions of the first substrate. These preliminary actions protect the substrate structure during subsequent cutting operations, preventing defects while enabling miniaturization.
2Device complexity
If integration degree is improved through multi-chip structure, then device functionality is enhanced, but manufacturing complexity increases
Solution Approach 1:
Multiple functional components (memory cells, circuit elements, bonding metal layers, insulating layers) are merged into a single integrated substrate structure. The first substrate integrates both bonding structures and circuit elements, while the second substrate integrates memory cells. This merging reduces the number of separate manufacturing steps compared to traditional multi-chip module approaches.
Solution Approach 2:
The patent transitions from planar integration to three-dimensional integration by stacking the first substrate with the second substrate vertically. Memory cells are arranged in three dimensions within the second substrate. This dimensional change increases integration density without proportionally increasing manufacturing complexity, as the stacking approach follows standard semiconductor fabrication processes.
3Reliability
If protective insulating layer extends to edge region, then cutting defects are reduced, but material usage increases
Solution Approach 1:
The protective insulating layer is selectively extended only to the edge regions of the first substrate where cutting defects are most likely to occur, rather than covering the entire substrate uniformly. This localized application provides maximum protection where needed while minimizing unnecessary material consumption in the inner regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances integration and reduces defects, enabling three-dimensional memory cell arrangements and efficient electrical connections, suitable for miniaturized and lightweight electronic components.
Implementation Method 1
second bonding metal layers respectively bonded to the first bonding metal layers
Data Source
AI summary
A semiconductor device includes a first chip structure including a wiring structure disposed on a circuit elements, and first bonding metal layers and a first bonding insulating layer on the wiring structure, an upper surface of the first chip structure having an edge region and an inner region surrounded by the edge region, a second chip structure disposed on an inner region of the upper surface of the first chip structure, and including second bonding metal layers respectively bonded to the first bonding metal layers, a second bonding insulating layer bonded to the first bonding insulating layer, and a memory cell layer on the second bonding metal layers and the second bonding insulating layer, an insulating capping layer disposed on an upper surface of the second chip structure and extending to the edge region, and a connection pad disposed on a region of the insulating capping layer.