3D Stacked Semiconductor Device for AI Processing
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Solution Overview
Problem
In AI technology, the repeated product-sum operations using weight data and input data lead to high heat generation and power consumption, with existing architectures like Binary Neural Networks and Ternary Neural Networks facing challenges in reducing arithmetic operation speed and power consumption due to increased wiring and parasitic capacitance.
Innovation Solution
A semiconductor device with a novel structure, comprising multiple memory circuits and an arithmetic circuit in separate layers, utilizing metal oxide transistors with In, Ga, and Zn, and silicon transistors, where memory circuits are stacked over the arithmetic and switching circuits to reduce wiring length and parasitic capacitance, enabling efficient data transfer and low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the number of parallel wirings between the memory cell array and the arithmetic circuit is increased to increase bandwidth, then the arithmetic operation speed is improved, but the area of the peripheral circuit increases greatly
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture, where memory cell arrays are positioned in different layers above the arithmetic circuit. This vertical stacking enables multiple memory blocks to share common bit lines and wiring resources, increasing effective bandwidth without proportionally increasing peripheral wiring area.
2Use of energy by moving object
If the bit line is shortened to reduce charge and discharge energy, then the power consumption is reduced, but the area of the peripheral circuits increases greatly due to alternating arrangement
Solution Approach 1:
By stacking memory cell arrays vertically in multiple layers above the arithmetic circuit, the patent shortens the horizontal bit line length connecting memory to arithmetic units. The vertical stacking allows memory blocks to be positioned closer to the arithmetic circuit in the vertical dimension, reducing the horizontal distance and thus the bit line length and associated energy consumption.
Solution Approach 2:
Multiple memory cell arrays in different layers share common bit lines and wiring structures. This merging of wiring resources across layers reduces the total amount of wiring required compared to having separate wiring for each memory block, thereby reducing peripheral circuit area while maintaining short bit line lengths.
3Length of moving object
If bonding technology is used to integrate transistors vertically to shorten bit lines, then the bit line length is reduced, but the intervals between connection portions are large causing increased parasitic capacitance
Solution Approach 1:
The patent divides the semiconductor device into multiple functional layers: an arithmetic circuit layer and multiple memory cell array layers stacked above. Each layer is independently optimized, with the arithmetic circuit layer containing processing units and the memory layers containing storage units. This segmentation allows for optimized inter-layer connections with minimal parasitic capacitance.
Solution Approach 2:
The patent introduces intermediate connection structures such as through-silicon vias (TSVs) and inter-layer wiring as mediators between the arithmetic circuit layer and memory cell array layers. These intermediary elements provide optimized electrical pathways that minimize parasitic capacitance while enabling vertical integration and short bit line lengths.
Data Source
AI summary
A semiconductor device with a novel structure is provided. A plurality of memory circuits, a switching circuit, and an arithmetic circuit are included. Each of the plurality of memory circuits has a function of retaining weight data and a function of outputting the weight data to a first wiring. The switching circuit has a function of switching a conduction state between any one of the plurality of first wirings and a second wiring. The arithmetic circuit has a function of performing arithmetic processing using input data and the weight data supplied to the second wiring. The memory circuits are provided in a first layer. The switching circuit and the arithmetic circuit are provided in a second layer. The first layer is provided in a layer different from the second layer.