Stacked Semiconductor Device with Through-Vias and RDL
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Solution Overview
Problem
The semiconductor industry faces challenges in further reducing the physical size of semiconductor devices while maintaining performance, as traditional packaging techniques struggle to keep pace with the miniaturization and integration demands driven by advancements in semiconductor technologies.
Innovation Solution
The development of stacked and bonded semiconductor devices, where active circuits are fabricated on separate substrates and then physically and electrically connected using advanced bonding techniques, along with the integration of through-substrate vias and redistribution layers to enhance connectivity and reduce device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional packaging techniques are used, then manufacturing process is simple, but device size cannot be further reduced
Solution Approach 1:
The patent transitions from planar packaging to three-dimensional stacked packaging, where multiple semiconductor dies are bonded vertically to form a stacked structure. This dimensional change enables continued size reduction by utilizing the vertical dimension for integration rather than expanding horizontally.
Solution Approach 2:
The patent divides the semiconductor device into multiple separate dies that are fabricated independently and then bonded together in a stacked configuration. This segmentation allows each die to be optimized for specific functions and enables higher integration density through vertical stacking.
2Productivity
If minimum feature size is reduced, then integration density improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary fabrication of multiple dies with their respective interconnect structures before bonding. Through-subsubstrate vias and redistribution layers are formed in advance on each die, allowing precise alignment and connection during the bonding process without requiring ultra-precise feature fabrication at the smallest dimensions.
Solution Approach 2:
The patent introduces redistribution layers and through-substrate vias as intermediary structures that facilitate precise electrical connections between stacked dies. These intermediary elements provide alignment tolerance and enable accurate routing of signals between layers without directly requiring sub-20nm precision for all interconnects.
3Volume of moving object
If stacked and bonded structure is implemented, then device size is reduced, but bonding process complexity increases
Solution Approach 1:
The patent combines multiple fabrication steps including via formation, dielectric deposition, and bonding into an integrated process flow. The through-substrate vias are formed through the entire die thickness before bonding, merging the via formation and bonding processes to reduce overall complexity.
Solution Approach 2:
The patent designs the stacked structure with universal bonding interfaces and standardized interconnect structures that can be applied across multiple dies. The through-substrate vias and redistribution layers serve multiple functions including electrical connection, mechanical alignment, and stress management, simplifying the overall bonding process.
Data Source
AI summary
A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device includes a first set of through vias between and connecting a top package and a redistribution layer (RDL), the first set of through vias in physical contact with a molding compound and separated from a die. The semiconductor device also includes a first interconnect structure between and connecting the top package and the RDL, the first interconnect structure separated from the die and from the first set of through vias by the molding compound. The first interconnect structure includes a second set of through vias and at least one integrated passive device.