Stacked Semiconductor Dice for High Density Memory
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Solution Overview
Problem
Semiconductor devices face challenges in increasing data storage density due to dense conductive lines causing capacitive loading and capacitive coupling, limiting further reduction in feature size and making it difficult to enhance data storage capacity.
Innovation Solution
The solution involves distributing memory device portions across multiple semiconductor dice in a stacked arrangement, with each die containing specific components like memory cells or support circuitry, and using different types of wafers to minimize parasitic capacitance and floating body effects, allowing for increased storage density within a given volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If features are shrunk to increase data storage capacity, then data storage density is improved, but capacitive loading and capacitive coupling increase causing poor device performance
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of memory cells to a three-dimensional stacked arrangement using multiple semiconductor dies. By stacking dies vertically with memory cells distributed across different layers (first die containing first and second memory cells, second die containing third and fourth memory cells), the invention increases storage capacity while maintaining larger feature sizes and reducing capacitive coupling effects that plague planar designs.
2Quantity of substance
If feature size is reduced to accommodate more memory cells, then data storage density is improved, but minimum achievable dimension is reached making further reduction unachievable
Solution Approach 1:
The invention moves from scaling in the lateral plane to scaling in the vertical dimension by stacking multiple semiconductor dies. This allows continued increase in storage density without further reducing the already-minimal feature dimensions of transistors and conductive lines within each die.
Solution Approach 2:
The memory device is segmented into multiple separate semiconductor dies, each containing a portion of the total memory capacity. This segmentation allows each individual die to maintain larger, more manufacturable feature sizes while the aggregate stack provides the desired high storage density.
3Quantity of substance
If conductive lines are increased to accommodate additional memory cells, then data storage capacity is improved, but total number of conductive lines becomes dense causing capacitive loading and capacitive coupling
Solution Approach 1:
By dividing the memory device into multiple separate dies, the patent segments the conductive line networks into distinct groups on different dies. This reduces the overall density of conductive lines within each die and minimizes parasitic capacitance and coupling effects that would occur in a single dense planar interconnect structure.
Solution Approach 2:
The invention distributes conductive lines across multiple vertical layers (different dies stacked together) rather than concentrating them in a single planar layer. This three-dimensional distribution of interconnects reduces line density and capacitive effects in any given cross-section.
Data Source
AI summary
Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice.