Stacked Semiconductor Die Package With Unique Address Traces
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in increasing memory density in flash memory cards is hindered by the limitations of stacking more memory chips due to the stress from encapsulation processes, which often results in die cracking, and the need to discard entire stacks if a single die is defective during testing.
Innovation Solution
A semiconductor package design featuring stacked and bonded layers of substrates with conductive traces and unique address layouts, allowing for direct bonding of semiconductor die to the substrate and selective addressing, eliminating the need for encapsulation and enabling individual die replacement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more memory die are stacked in a single package, then memory density is increased, but the stress from encapsulation causes die cracking
Solution Approach 1:
The patent divides the substrate into multiple separate carrier substrates, each carrying one or more memory die. This segmentation allows each die to be independently supported and tested, eliminating the risk that a defect in one die compromises the entire stack. The carrier substrates act as independent carriers that can be selectively bonded together based on test results.
Solution Approach 2:
The patent implements testing of memory die before final stacking and packaging. By performing preliminary testing on individual die mounted on carrier substrates, defective die can be identified and excluded from the final package. This preliminary action prevents the need to discard entire stacks due to a single defective die.
2Object-affected harmful factors
If traditional encapsulation is used, then die are protected, but high injection force causes stress and die cracking
Solution Approach 1:
The patent removes the traditional encapsulation molding compound from the packaging process. Instead of enclosing all die in a single encapsulant that requires high injection force, the invention uses open carrier substrates that mechanically support the die without requiring high-stress encapsulation. This extraction of the encapsulation step eliminates the associated stress and cracking problems.
Solution Approach 2:
The patent introduces carrier substrates as intermediary elements between the memory die and the final package structure. These carrier substrates provide mechanical support, protection, and electrical connections without requiring high-force encapsulation. The carrier substrates act as mediators that protect the die through gentle mechanical bonding rather than high-stress molding.
3Reliability
If die are tested after stacking, then system functionality is verified, but defective die require discarding entire stacks
Solution Approach 1:
The patent segments the testing process to operate at the individual die level rather than at the stack level. Each die mounted on a carrier substrate can be independently tested and identified as good or defective. This segmentation enables selective retention of good die and discarding of only defective individual die, rather than requiring disposal of entire stacks.
Solution Approach 2:
The patent applies different treatments to different local regions (individual die) based on their test results. Good die are selected for inclusion in the final package, while defective die are discarded locally without affecting other good die in the same stack. This local quality approach maximizes the utilization of good die and minimizes waste.
4Quantity of substance
If higher density memory chips are used, then memory capacity increases, but manufacturing complexity and cost increase
Solution Approach 1:
The patent creates a universal carrier substrate platform that can accommodate multiple types and densities of memory die. The same carrier substrate design and bonding process can be used regardless of the specific memory die being packaged. This universality simplifies manufacturing by providing a standardized process that works with various memory chip types, reducing the complexity associated with handling higher density chips.
Data Source
AI summary
A semiconductor package is disclosed including a plurality semiconductor die mounted on stacked and bonded layers of substrate, for example polyimide tape used in tape automated bonding processes. The tape may have a plurality of repeating patterns of traces and contact pads formed thereon. The traces each include aligned interconnect pads on the respective top and bottom surfaces of the substrate for bonding the traces of one pattern to the traces of another pattern after the patterns have been singulated from the substrate, aligned and stacked. Semiconductor die such as flash memory and a controller die are mounted on the traces of the respective patterns on the substrate. In order for the controller die to uniquely address a specific flash memory die in the stack, a group of traces on each substrate supporting the memory die are used as address pins and punched in a unique layout relative to the layout of the traces other substrates. By providing each flash memory semiconductor die on a substrate with a unique layout of address traces, each memory die may be selectively addressed by the controller die.