Stacked Semiconductor Layers for High-Resolution Display Devices
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Solution Overview
Problem
The challenge is to design a high-resolution display device that minimizes the degradation of display quality by efficiently arranging transistors and storage capacitors within a limited space in organic light emitting diode displays, while reducing the impact of these elements on transistor characteristics.
Innovation Solution
The display device incorporates a specific layered structure with semiconductor patterns, conductive layers, and insulating layers, including a substrate with semiconductor patterns, conductive layers, and insulating layers, where the upper semiconductor layer does not overlap the gate electrode or initialization power line, allowing for efficient space utilization and reduced interference, and includes a unique arrangement of connection patterns and contact plugs to connect electrodes and power lines effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If transistors and storage capacitors are arranged within a limited space to achieve high-resolution display, then display resolution is improved, but transistor characteristics deteriorate due to increased element density and interference
Solution Approach 1:
The patent utilizes multi-layer stacking to arrange transistors and storage capacitors in different vertical layers rather than planar arrangement. The first transistor is formed in a first active layer, the second transistor in a second active layer, and the storage capacitor in a third active layer, effectively using the third dimension to increase component density while maintaining adequate spacing and reducing interference between elements.
Solution Approach 2:
The patent divides the display structure into multiple stacked layers, with each layer containing specific components. The first conductive layer contains the first transistor, the second conductive layer contains the second transistor, and the third conductive layer contains the storage capacitor. This segmentation allows independent optimization of each layer's layout and reduces parasitic interactions between components.
2Manufacturing precision
If multiple transistors and capacitors are integrated in a compact pixel structure, then pixel density is improved, but the area occupied by supporting elements increases
Solution Approach 1:
The patent stacks multiple functional layers vertically to fit more components within the same planar footprint. By placing the first transistor, second transistor, and storage capacitor in different vertical layers (first, second, and third conductive layers respectively), the design achieves high pixel density without proportionally increasing the horizontal area occupied by each pixel.
Solution Approach 2:
The patent implements a nested structure where the first transistor and second transistor are positioned to overlap in the planar view, with one transistor located above the other in the vertical stacking direction. The storage capacitor is nested within the same pixel region, utilizing the vertical space between and around other components to minimize the overall pixel area.
Data Source
AI summary
A display device includes first semiconductor pattern including a first channel portion, a first electrode connected to a driving voltage line, and a second electrode connected to a light emitting element, a first insulating, a first conductive layer including a first gate electrode, a second insulating layer, a second conductive layer including an initialization power line, a third insulating layer, an upper semiconductor layer including a second semiconductor pattern including a second channel portion, a third electrode, and a fourth electrode connected to the first gate electrode, and a third semiconductor pattern including a third channel portion, a fifth electrode connected to the third electrode, and a sixth electrode connected to the second electrode, a fourth insulating layer, and a third conductive layer including a scan line and a control signal line, wherein the upper semiconductor layer does not overlap the first gate electrode and the initialization power line.