Stacked Semiconductor Package With Dummy Chip Mediator
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing stacked semiconductor packages face challenges in efficiently stacking semiconductor chips of varying sizes, as they require uniform size for easy integration, which can reduce yield and increase manufacturing costs due to the need for wafer design changes.
Innovation Solution
A stacked semiconductor package design where a mold layer is used to adjust the size of smaller chips to match larger ones, allowing for vertical stacking with penetration electrodes for electrical connection, enabling the integration of chips of different sizes without altering the wafer design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If semiconductor chips of various sizes are stacked directly without size adjustment, then manufacturing flexibility and yield are improved, but stacking difficulty increases due to size mismatch
Solution Approach 1:
A dummy chip is introduced as an intermediary component between the smaller first semiconductor chip and the larger second semiconductor chip. The dummy chip has a size that matches the larger chip, allowing the smaller chip to be stacked on it. This mediator enables size-mismatched chips to be stacked together without requiring size adjustment of the actual semiconductor chips, thus maintaining manufacturing flexibility while solving the stacking difficulty.
2Ease of manufacture
If a peripheral region is added to smaller chips to match larger chip sizes, then stacking ease is improved, but yield decreases due to wafer design constraints
Solution Approach 1:
Instead of adding peripheral regions to the actual semiconductor chips (which would reduce yield), a separate dummy chip is used as a mediator. The dummy chip is formed from wafer material and can be optimized independently, allowing the actual semiconductor chips to maintain their original sizes and maximize yield per wafer while still enabling easy stacking through the dummy chip intermediary.
Solution Approach 2:
The stacking structure is segmented into three distinct components: the first semiconductor chip, the dummy chip, and the second semiconductor chip. This segmentation allows each component to be optimized independently - the semiconductor chips for their functional requirements and the dummy chip for size matching - thereby achieving both stacking ease and high yield.
3Ease of manufacture
If uniform chip sizes are used in stacked packages, then stacking ease is improved, but design flexibility and cost increase due to wafer design changes
Solution Approach 1:
The dummy chip serves as a size-matching intermediary that allows semiconductor chips of different sizes to be stacked without requiring uniform chip sizes. This eliminates the need for wafer design changes to create uniform chips, thereby maintaining design flexibility and reducing manufacturing costs while still achieving easy stacking.
Data Source
AI summary
Disclosed herein is a stacked semiconductor package in which semiconductor chips having various sizes are stacked. In accordance with one aspect of the present disclosure, a stacked semiconductor package includes a first semiconductor chip structure provided with a first semiconductor chip, a first mold layer surrounding the first semiconductor chip, and a first penetration electrode passing through the first mold layer and electrically connected to the first semiconductor chip, and a second semiconductor chip structure vertically stacked on the first semiconductor chip structure and provided with a second semiconductor chip and a second penetration electrode electrically connected to the first penetration electrode, wherein the first semiconductor chip structure may have the same size as the second semiconductor chip structure.