3D Stacked Semiconductor Error Detection via Coupling Vias
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Solution Overview
Problem
Existing semiconductor devices face limitations in error detection and correction due to the number of signals that can be compared being restricted by the number of pins on the semiconductor chip.
Innovation Solution
A semiconductor structure comprising two chips with a comparing circuit that allows indirect and direct signal reception between electric nodes, enabling the assertion of mismatch signals and overcoming pin limitations through the use of coupling vias and error checking layers for enhanced error detection and correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If identical semiconductor chips are connected via printed wires on a board for error detection and correction, then error detection capability is improved, but the number of comparable signals is limited by the number of pins on the semiconductor chip
Solution Approach 1:
The patent transitions from a two-dimensional planar connection (chips on a board connected via printed wires) to a three-dimensional vertical stacking architecture. By stacking chips vertically and using through-silicon vias (TSVs) for inter-layer connections, the system enables multiple signal paths between chips without increasing the lateral pin count on each chip, thereby overcoming the limitation of comparable signals while maintaining error detection capability
Solution Approach 2:
The patent introduces an intermediate error detection layer positioned between the stacked semiconductor chips. This intermediate layer contains comparison circuits that receive signals from multiple chips through TSVs and perform error detection. The intermediate layer acts as a mediator that enables comprehensive signal comparison without requiring direct pin-to-pin connections between all chips, thus increasing the number of comparable signals while maintaining system reliability
Data Source
AI summary
A semiconductor structure and a method for operating the same. The semiconductor structure includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip is on top of and bonded to the second semiconductor chip. The first and second semiconductor chips include a first and a second electric nodes. The second semiconductor chip further includes a first comparing circuit. The semiconductor structure further includes a first coupling via electrically connecting the first electric node of the first semiconductor chip to the first comparing circuit of the second semiconductor chip. The first comparing circuit is capable of (i) receiving an input signal from the second electric node directly, (ii) receiving an input signal from the first electric node indirectly through the first coupling via, and (iii) asserting a first mismatch signal in response to the input signals from the first and second electric nodes being different.