Stacked Semiconductor Package with Fan-Out Redistribution Layers
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Solution Overview
Problem
The increasing demand for data processing in electronic products necessitates higher semiconductor integration, which is challenging due to limitations in current semiconductor integration technology, requiring multiple semiconductor chips to be packaged together while maintaining a designated size for specific applications.
Innovation Solution
A semiconductor package design that includes a substrate with redistribution conductive layers and interconnectors connecting multiple main semiconductor chips to a sub semiconductor chip, allowing for efficient signal exchange and stable stacking, utilizing fan-out technology to redistribute sub chip pads along the edges of the sub semiconductor chip for improved connectivity and operation characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor chips are embedded in one semiconductor package to increase integration, then the degree of integration is improved, but the device complexity increases
Solution Approach 1:
The patent divides the semiconductor package into multiple independent chip stacks, where each stack contains one or more main semiconductor chips connected to the substrate through dedicated interconnectors. This segmentation allows each chip stack to be independently designed and connected, simplifying the overall system architecture while achieving high integration through the stacking of multiple chips vertically on the substrate
Solution Approach 2:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture. By connecting multiple semiconductor chips vertically through interconnectors rather than arranging them side-by-side on the substrate, the design achieves higher integration density without proportionally increasing the substrate area, thereby managing device complexity more effectively
2Productivity
If multiple semiconductor chips are stacked to increase integration, then the data processing capability is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent segments the interconnection system into separate interconnectors for each chip stack, with each interconnector independently connecting a specific main semiconductor chip to the substrate. This segmentation allows for independent alignment and connection processes, reducing the cumulative precision requirements that would arise from attempting to connect all chips in a single complex interconnection system
Solution Approach 2:
The substrate serves as an intermediary platform that provides standardized connection points (substrate pads) for each chip stack. The interconnectors act as mediator elements that facilitate precise alignment and connection between the chips and substrate, enabling modular assembly where each chip can be positioned and connected independently rather than requiring simultaneous precision alignment of all chips
3Adaptability or versatility
If fan-out technology is used to redistribute sub chip pads, then the connectivity is improved, but the wiring structure complexity increases
Solution Approach 1:
The patent merges the redistribution function into the sub semiconductor chip package structure itself. The sub chip pads are redistributed along the edges of the sub semiconductor chip and connected to the substrate through the sub package interconnectors, combining the packaging and signal redistribution functions into a unified structure that simplifies the overall wiring architecture
Solution Approach 2:
The patent redistributes the sub chip pads from their original positions on the sub semiconductor chip to new positions along the edges of the sub molding layer in the horizontal plane. This two-dimensional redistribution on the substrate plane, rather than requiring three-dimensional wiring through the chip stack, simplifies the wiring structure while achieving improved connectivity
Data Source
AI summary
A semiconductor package includes: a substrate having first substrate pads formed at one side edge thereof in a first direction and second substrate pads formed at an other side edge thereof in the first direction; a sub semiconductor package formed on the substrate, and including a sub semiconductor chip, a sub molding layer which surrounds side surfaces of the sub semiconductor chip and redistribution conductive layers which extend onto the sub molding layer while being connected with sub chip pads of the sub semiconductor chip and are connected to first redistribution pads and second redistribution pads formed at one side edge and the other side edge, respectively, of the sub molding layer in the first direction; a first chip stack formed on the sub semiconductor package, and including first main semiconductor chips; and a second chip stack formed on the first chip stack, and including second main semiconductor chips.