Stacked Semiconductor Fin Structures for Independent N/P Control
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Solution Overview
Problem
Existing planar GAA finFETs face challenges in independently controlling nanosheet/nanowire dimensions and spacings for n-type and p-type devices, requiring different work function metal fills and spacer materials, leading to performance degradation and complexity in manufacturing.
Innovation Solution
The development of vertically stacked and crossover-stacked semiconductor devices with independently controlled fin structures, including rotated gates, allows for separate management of nanosheet/nanowire dimensions and spacings, and incorporates isolation layers to enhance device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If planar GAA finFETs use different work function metal fills and spacer materials for n-type and p-type devices, then device performance can be optimized, but manufacturing complexity increases
Solution Approach 1:
The patent divides the device structure into vertically stacked fin structures, where each fin can be independently controlled. This segmentation allows different work function metal fills and spacer materials to be applied to specific fins (n-type or p-type) without affecting the entire device, thereby optimizing performance while managing manufacturing complexity through modular processing steps.
Solution Approach 2:
The patent implements local quality by enabling different material compositions and dimensions for specific fins within the same device. Through selective fin formation processes, n-type fins can have different work function metals and spacer materials compared to p-type fins, allowing localized optimization of device performance without requiring complex global processing changes.
2Reliability
If nanosheet/nanowire dimensions and spacings are independently controlled for n-type and p-type devices, then device performance is enhanced, but manufacturing process complexity increases
Solution Approach 1:
The patent segments the nanosheet/nanowire structures into distinct groups associated with different fin types. By forming nanosheets/nanowires in association with specific fins during sequential fin formation processes, the patent enables independent dimensional and spacing control for n-type and p-type devices while maintaining a unified manufacturing flow that avoids excessive complexity.
Solution Approach 2:
The patent applies preliminary action by pre-defining the dimensional and spacing characteristics of nanosheets/nanowires during the fin formation process itself. Through controlled deposition and etching steps performed before final device assembly, the patent establishes distinct nanosheet/nanowire geometries for different fin types, simplifying subsequent manufacturing steps while achieving the desired performance optimization.
3Object-affected harmful factors
If vertically stacked and crossover-stacked configurations are used, then parasitic resistance and capacitance are reduced, but device structure complexity increases
Solution Approach 1:
The patent transitions from planar to vertically stacked configurations, utilizing the vertical dimension to reduce parasitic effects. By stacking fins and their associated nanosheets/nanowires vertically, the patent shortens current paths and reduces parasitic resistance and capacitance while maintaining a compact footprint. The crossover-stacked configuration further optimizes this by alternating fin orientations to minimize interconnect parasitics.
Solution Approach 2:
The patent merges multiple functional elements into the vertical stack structure, combining fins, nanosheets, nanowires, and isolation layers into an integrated three-dimensional architecture. This merging reduces the overall device footprint and minimizes parasitic effects by bringing source, drain, and channel regions closer together in the vertical dimension, thereby reducing parasitic resistance and capacitance despite the increased structural complexity.
Data Source
AI summary
The present disclosure describes a semiconductor device includes a first fin structure, an isolation structure in contact with a top surface of the first fin structure, a substrate layer in contact with the isolation structure, an epitaxial layer in contact with the isolation structure and the substrate layer, and a second fin structure above the first fin structure and in contact with the epitaxial layer.