Stacked Semiconductor Gate Electrodes with Tapered Insulation
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Solution Overview
Problem
The integration density of two-dimensional semiconductor memory devices is limited by high manufacturing costs and the difficulty in forming fine patterns, which restricts the increase in cost-effectiveness.
Innovation Solution
A method of fabricating semiconductor devices involves forming insulation structures with vertically stacked insulation patterns and gap regions, where conductive layers are deposited using atomic layer deposition, and isotropically etched to form gate electrodes with uniform width, ensuring consistent thickness and reliability across the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional semiconductor memory devices use fine patterns to increase integration density, then integration density is improved, but manufacturing costs increase and manufacturing complexity increases
Solution Approach 1:
The patent transitions from two-dimensional planar memory structures to three-dimensional vertically stacked structures. Multiple insulation patterns are stacked vertically with gap regions between them, allowing gate electrodes to be formed in the vertical dimension rather than requiring finer lateral patterning. This dimensional transition enables increased integration density without proportionally increasing manufacturing complexity.
Solution Approach 2:
The memory structure is segmented into multiple vertically stacked insulation patterns separated by gap regions. Each insulation pattern can be independently formed and controlled, allowing the complex three-dimensional structure to be built through repeated application of simpler formation processes rather than requiring a single complex lithography step.
2Manufacturing precision
If two-dimensional semiconductor memory devices use fine patterns to increase integration density, then integration density is improved, but device complexity increases
Solution Approach 1:
The patent resolves device complexity by moving the integration challenge from the lateral dimension to the vertical dimension. Instead of packing more cells in the planar area through finer lithography, the structure stacks multiple insulation patterns and gate electrodes vertically, simplifying the lateral patterning requirements while achieving higher integration density.
3Reliability
If conductive layers are deposited conformally on tapered insulation structures, then coverage is improved, but gate electrode width uniformity deteriorates
Solution Approach 1:
The patent applies a preliminary etching step to the conformally deposited conductive layers before finalization. This preliminary action removes the thickness variation introduced by conformal deposition on tapered surfaces, restoring uniform gate electrode widths while maintaining the beneficial coverage and filling of the gap regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the integration density and reliability of semiconductor devices by maintaining uniform gate electrode widths and thickness, reducing manufacturing costs and improving device performance.
Implementation Method 1
forming a first conductive layer filling the gap regions and covering two opposite sidewalls of the insulation structure, and forming a second conductive layer covering the first conductive layer. The second conductive layer and the seed layer may be formed using an atomic layer deposition process.
Data Source
AI summary
Semiconductor devices and methods of fabricating semiconductor devices that may include forming an insulation structure including insulation patterns that are sequentially stacked and vertically separated from each other to provide gap regions between the insulation patterns, forming a first conductive layer filling the gap regions and covering two opposite sidewalls of the insulation structure, and forming a second conductive layer covering the first conductive layer. A thickness of the second conductive layer covering an upper sidewall of the insulation structure is greater than a thickness of the second conductive layer covering a lower sidewall of the insulation structure.