3D Stacked Semiconductor Contact Structure for Gate-Safe SAC
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Solution Overview
Problem
Current semiconductor device fabrication techniques face challenges in increasing integration and reliability, particularly in three-dimensionally stacked devices, where misalignment during the self-aligned contact (SAC) process can damage the upper gate electrode.
Innovation Solution
The semiconductor device incorporates a self-aligned contact (SAC) process that forms the upper contact by penetrating the upper semiconductor substrate and interlayer insulation film, with a design that includes a first portion penetrating the substrate and a second portion with a side surface adjacent to the upper gate structure, ensuring protection of the gate electrode and enhancing integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a self-aligned contact (SAC) process is used to form the upper contact in a three-dimensionally stacked semiconductor device, then the alignment precision between the upper contact and upper gate structure is improved, but the risk of damage to the upper gate electrode during the SAC process increases
Solution Approach 1:
The upper contact is formed to protrude from the first surface of the upper semiconductor substrate before the SAC process is performed. This preliminary positioning ensures that the upper contact is already in the correct location and reduces the risk of misalignment during the SAC process, thereby improving alignment precision without increasing the risk of damage to the upper gate electrode
Solution Approach 2:
The upper contact is designed with a protruding structure that extends from the first surface of the upper semiconductor substrate. This protruding design acts as a cushioning structure that prevents direct contact between the SAC process tools and the upper gate electrode, thereby protecting the gate electrode from damage while maintaining alignment precision
2Ease of manufacture
If the upper contact is formed to penetrate the upper semiconductor substrate with a uniform width, then the manufacturing process is simplified, but the protection effect on the upper gate electrode is reduced
Solution Approach 1:
The upper contact is divided into two distinct portions: a first portion that penetrates the upper semiconductor substrate and a second portion that protrudes from the first surface. This segmentation allows the second portion to serve as a protective structure for the upper gate electrode while the first portion maintains electrical connection, thereby improving reliability without significantly complicating the manufacturing process
Solution Approach 2:
The upper contact is designed with different widths at different locations: the first portion has a width that allows it to penetrate the substrate, while the second portion has a reduced width that allows it to fit alongside the upper gate structure. This local variation in dimensions provides protection to the gate electrode while maintaining ease of manufacture through standard fabrication techniques
3Reliability
If the width of the upper contact decreases toward the second surface, then the protection effect on the upper gate electrode is improved, but the manufacturing precision requirement increases
Solution Approach 1:
The upper contact is formed with a tapered width profile in advance, with the width decreasing from the first surface toward the second surface. This preliminary shaping is achieved through standard fabrication techniques such as angled etching or deposition, which provide sufficient protection to the upper gate electrode without requiring extremely high manufacturing precision
Solution Approach 2:
The width of the upper contact is varied as a continuous parameter from the first surface to the second surface, creating a gradual taper rather than an abrupt change. This parameter change approach improves the protection effect on the upper gate electrode by providing a smoother transition that is easier to manufacture with standard precision tolerances
Data Source
AI summary
A semiconductor device including: a lower semiconductor substrate; an upper semiconductor substrate overlapping the lower semiconductor substrate, the upper semiconductor substrate including a first surface and a second surface opposite to the first surface; an upper gate structure on the first surface of the upper semiconductor substrate; a first interlayer insulation film which covers the upper gate structure, wherein the first interlayer insulation film is between the lower semiconductor substrate and the upper semiconductor substrate; and an upper contact connected to the lower semiconductor substrate, wherein the upper contact is on a side surface of the upper gate structure, wherein the upper contact includes a first portion penetrating the upper semiconductor substrate, and a second portion having a side surface adjacent to the side surface of the upper gate structure, and a width of the first portion decreases toward the second surface.