Stacked Semiconductor Device Half-Dicing Resin Sealing
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Solution Overview
Problem
Current chip-stacking technologies for semiconductor devices involve complex fabrication processes that compromise product quality due to defects and inefficiencies in connecting semiconductor chips, particularly in the dicing and resin sealing steps.
Innovation Solution
A method involving half-dicing of semiconductor wafers, connecting pads with conductive connectors, sealing with resin, grinding to separate chips, and stacking on a wiring substrate with electrical connection using conductive members, while improving connector conductivity through plasma etching or soldering, to simplify the process and enhance product quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional chip-stacking technology is used with complete dicing and separate connection processes, then chip connectivity is achieved, but the fabrication process becomes complicated and product quality deteriorates
Solution Approach 1:
The patent applies preliminary action by performing half-dicing before resin sealing, creating dicing grooves that guide subsequent complete dicing. This preliminary structuring allows the resin to properly seal around conductive connectors while maintaining chip integrity, eliminating the need for complex post-sealing connection processes and reducing fabrication complexity
Solution Approach 2:
The patent merges the sealing and connection functions by embedding conductive connectors within the resin sealant material itself. The resin serves dual purposes: providing mechanical sealing and enabling electrical connection through the embedded conductive elements, thereby simplifying the overall fabrication process while maintaining reliability
2Reliability
If dicing grooves are completely filled with resin, then sealing is improved, but chip separation becomes difficult and manufacturing precision deteriorates
Solution Approach 1:
The patent applies local quality by creating a non-uniform resin distribution within the dicing grooves. The resin is positioned to seal around the conductive connectors and bond chips together, while deliberately leaving the central channel open. This localized sealing approach ensures both adequate sealing quality and easy chip separation along the groove lines
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the fabrication process, ensures insulation and electrical integrity, and prevents defects during chip separation and connection, thereby improving the quality and reliability of semiconductor chip stacks.
Implementation Method 1
exposing the ends of the conductive connectors from the semiconductor chip stack by plasma etching
Data Source
AI summary
A method of manufacturing a semiconductor device includes: (a) half-dicing a semiconductor wafer including plural semiconductor chips, thereby forming dicing grooves in the semiconductor wafer, wherein each semiconductor chip includes a circuit and pads and wherein the semiconductor wafer includes: a first surface on which the circuit and the pads are formed; and a second surface opposite to the first surface, (b) connecting the pads to each other by conductive connectors; (c) sealing the first surface of the semiconductor wafer, the dicing grooves and the conductive connectors with a resin; (d) grinding the second surface of the semiconductor wafer, thereby forming a group of sealed chips; (e) dividing the group of sealed chips into individual sealed chips; (f) mounting and stacking the individual sealed chips on a wiring substrate having connection terminals thereon; and (g) electrically-connecting the conductive connectors and the connection terminals using a conductive member.