Stacked Semiconductor Interconnect Layout for Power and High-Speed Signals
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Solution Overview
Problem
Existing three-dimensional semiconductor devices face challenges in achieving higher-capacity data processing with smaller form factors while maintaining structural integrity and optimizing electrical connections between stacked semiconductor structures.
Innovation Solution
The semiconductor device incorporates a design where the area of low-frequency signal conductive patterns is larger than high-frequency signal conductive patterns, with a greater number of connection electrodes for low-frequency signals to reduce resistance and a smaller number/effective area for high-frequency signals to minimize capacitance, enhancing power supply capability and high-speed signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the area of conductive patterns is increased to reduce resistance for low-frequency signals, then power supply capability is improved, but the device area occupied increases
Solution Approach 1:
The patent transitions from planar conductive patterns to three-dimensional stacked conductive patterns arranged vertically. Multiple conductive patterns are positioned at different heights along the vertical axis, enabling electrical connections between stacked semiconductor structures while minimizing the horizontal footprint. This vertical arrangement allows the device to maintain compact form factor while providing sufficient conductive cross-section area for low-frequency power signals.
Solution Approach 2:
The patent applies different design characteristics to different frequency domains within the same device. Low-frequency power signal paths are designed with larger conductive cross-sections and more connection electrodes to minimize resistance, while high-frequency signal paths use smaller conductive areas to reduce capacitance. This differentiated local optimization resolves the contradiction by tailoring conductive pattern geometry to the specific electrical requirements of each signal type.
2Reliability
If the number of connection electrodes is increased to reduce contact resistance, then electrical connection reliability is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent utilizes the vertical dimension to stack multiple semiconductor structures with corresponding conductive patterns at different heights. Connection electrodes are arranged in vertical columns passing through multiple layers, establishing electrical connections between stacked devices. This vertical stacking approach increases the number of connection points without proportionally increasing planar complexity, as the additional connections are organized along the vertical axis rather than requiring expanded lateral routing.
Solution Approach 2:
The patent designs conductive patterns and connection electrodes that serve multiple functions simultaneously. The same vertical connection electrode structure provides electrical pathways for both power delivery and signal transmission between stacked semiconductor structures. This multi-functional design reduces overall device complexity by eliminating the need for separate dedicated structures for different electrical functions.
3Speed
If the area of high-frequency signal conductive patterns is reduced to minimize capacitance, then signal transmission speed is improved, but the current carrying capacity decreases
Solution Approach 1:
The patent implements frequency-dependent conductive pattern design where the geometry and area of conductive patterns are optimized according to the frequency characteristics of the signals they carry. High-frequency signal paths use smaller conductive cross-sections to minimize parasitic capacitance and enable faster signal transmission, while low-frequency power paths use larger cross-sections to minimize resistance and maximize current carrying capacity. This local optimization resolves the contradiction by matching conductive pattern characteristics to the specific requirements of each frequency domain.
Data Source
AI summary
A semiconductor device may include: a first substrate; a first high-frequency signal through electrode and a first low-frequency signal through electrode passing through the first substrate; a first high-frequency signal conductive pattern and a first low-frequency signal conductive pattern respectively connected to the first high-frequency signal through electrode and the first low-frequency signal through electrode; and one or more first high-frequency signal connection electrodes and one or more first low-frequency signal connection electrodes respectively connected to the first high-frequency signal conductive pattern and the first low-frequency signal conductive pattern, wherein an area of the first low-frequency signal conductive pattern is larger than an area of the first high-frequency signal conductive pattern.