Stacked Semiconductor Interconnects via Conductive Plugs
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving smaller form factors, higher integration density, and lower power consumption as demand increases for miniaturization, higher speed, and greater bandwidth, which existing packaging techniques struggle to address effectively.
Innovation Solution
The method involves forming stacked semiconductor devices by bonding two semiconductor wafers using techniques like direct bonding, with the creation of interconnect structures such as conductive plugs that connect active circuits across the wafers, reducing the form factor and power consumption by providing an electrically conductive path between stacked wafers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional packaging techniques are used, then manufacturing simplicity is maintained, but integration density and form factor reduction are limited
Solution Approach 1:
The patent transitions from planar packaging to three-dimensional stacked packaging, where multiple semiconductor wafers are bonded vertically to form a stacked device. This dimensional change enables higher integration density by utilizing the vertical space rather than expanding horizontally, allowing more functional circuits to be integrated within a smaller footprint area.
Solution Approach 2:
The patent divides the semiconductor device into multiple separate wafers that are processed independently and then bonded together. Each wafer can contain specific functional circuits (e.g., logic circuits on one wafer, memory on another), allowing for modular design, independent optimization of each layer, and flexible integration of different circuit types to achieve higher overall integration density.
2Area of stationary object
If wafer stacking is implemented, then form factor is reduced, but bonding process complexity increases
Solution Approach 1:
The patent performs preliminary processing on each wafer before stacking, including forming through-silicon vias (TSVs) and conductive plugs during the individual wafer fabrication process. This preliminary action ensures that interconnect structures are already in place before bonding, simplifying the overall manufacturing process by eliminating the need for complex post-bonding interconnect formation and enabling direct electrical connections between stacked wafers.
Solution Approach 2:
The patent introduces conductive plugs and TSV structures as intermediary elements that facilitate electrical connection between stacked wafers. These intermediary conductive structures serve as mediators that bridge the electrical interfaces between different wafer layers, enabling straightforward bonding processes while maintaining reliable electrical connectivity through the stacked configuration.
3Reliability
If conductive plugs are formed through substrate, then electrical connectivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent forms conductive plugs and TSV structures during the standard CMOS fabrication process on each individual wafer before stacking. This preliminary formation ensures precise alignment and dimensional control using established lithography and etching processes, reducing the precision requirements for subsequent bonding operations while guaranteeing reliable electrical connectivity between stacked layers.
Solution Approach 2:
The patent optimizes the dimensions, materials, and formation parameters of conductive plugs and TSV structures to achieve reliable electrical connectivity. By carefully controlling parameters such as TSV diameter, wall thickness, conductive material composition, and plug depth, the patent ensures robust electrical connections while maintaining compatibility with standard manufacturing processes and minimizing precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher integration density, smaller form factors, cost-effectiveness, and reduced power consumption by creating efficient interconnect structures within stacked semiconductor devices.
Implementation Method 1
Two semiconductor wafers may be bonded together through suitable bonding techniques. The commonly used bonding techniques include direct bonding, chemically activated bonding, plasma activated bonding, anodic bonding, eutectic bonding, glass frit bonding, adhesive bonding, thermo-compressive bonding, reactive bonding and/or the like.
Data Source
AI summary
A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component.