Stacked Semiconductor Device Interface Chip Mounting
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Solution Overview
Problem
The existing semiconductor memory devices with stacked memory chips face challenges in miniaturization, increased manufacturing costs, and reduced development efficiency due to the need for a larger lowermost memory chip to accommodate interface circuits, which also leads to issues with thermal expansion and warpage, affecting electrical connections and reliability.
Innovation Solution
A semiconductor device configuration where the interface chip is mounted on the uppermost memory chip, and the lowermost memory chip is thicker to reduce warpage and stress, eliminating the need for through electrodes in the lowermost chip, and using spacers and specific electrode materials to improve connectivity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the interface circuit is incorporated in the lowermost memory chip, then data communication function is achieved, but the size of the lowermost memory chip increases and device size increases
Solution Approach 1:
The device is divided into separate functional modules: memory chips for storage and an interface chip for data communication. The interface chip is mounted on the uppermost memory chip, separating the interface circuit from the memory chips and allowing each component to be optimized independently, thus reducing overall device size while maintaining full functionality.
Solution Approach 2:
The interface chip is mounted in the vertical direction (Z-axis) on top of the uppermost memory chip rather than expanding the footprint in the horizontal plane. This three-dimensional stacking approach enables addition of communication functionality without increasing the device's planar area.
2Adaptability or versatility
If two types of memory chips are used (with and without interface circuit), then interface functionality is achieved, but development efficiency deteriorates and manufacturing cost increases
Solution Approach 1:
The system is segmented into standardized memory chips and a separate interface chip. All memory chips share the same design and specifications, while the interface chip handles communication protocols. This standardization eliminates the need to develop and manufacture multiple types of memory chips, improving development efficiency and reducing costs.
Solution Approach 2:
The interface chip serves as a universal component that can be mounted on various memory chips to provide data communication functionality. This multi-functional approach allows a single interface chip design to work with different memory chip configurations, reducing the need for custom modifications and improving manufacturing efficiency.
3Adaptability or versatility
If the lowermost memory chip size is increased to accommodate interface circuit, then interface function is achieved, but manufacturing cost increases and development efficiency decreases
Solution Approach 1:
By separating the interface circuit into a dedicated interface chip mounted on the uppermost memory chip, the lowermost memory chip maintains its standard size and design. This segmentation allows for economies of scale in manufacturing standardized memory chips, reducing per-unit costs and simplifying the supply chain.
Solution Approach 2:
Instead of integrating the interface circuit into the memory chip (conventional approach), the patent inverts the architecture by placing the interface chip separately on top of the memory stack. This inversion allows standard memory chips to be manufactured independently and then combined with the interface chip, reducing manufacturing complexity and cost.
4Speed
If through electrodes are provided in all memory chips for electrical connection, then high-speed data transmission is achieved, but device complexity and manufacturing cost increase
Solution Approach 1:
The electrical connection structure is segmented such that through electrodes are provided only in the uppermost memory chip where the interface chip is mounted, rather than in all memory chips. The interface chip establishes electrical connections to the memory chips through bump electrodes, simplifying the overall connection structure while maintaining high-speed data transmission capability.
Solution Approach 2:
The function of providing through electrodes for electrical connection is extracted from the memory chips and consolidated into the uppermost memory chip and interface chip. This extraction reduces the complexity of manufacturing and assembling through electrodes in every memory chip, while the interface chip's bump electrodes provide the necessary electrical pathways for high-speed communication.
Data Source
AI summary
In one embodiment, a semiconductor device includes a chip stacked body disposed on an interposer substrate and an interface chip mounted on the chip stacked body. The chip stacked body has plural semiconductor chips, and is electrically connected via through electrodes provided in the semiconductor chips excluding a lowermost semiconductor chip in a stacking order of the plural semiconductor chips and bump electrodes. The interface chip is electrically connected to the interposer substrate via a rewiring layer formed on a surface of an uppermost semiconductor chip in the stacking order or through electrodes provided in the interface chip.