3D Stacked Semiconductor Package With Integrated Passive Devices
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Solution Overview
Problem
The semiconductor industry faces challenges in further reducing the physical size of semiconductor devices while maintaining performance, as traditional bonding processes are inefficient and do not adequately address the need for smaller, more creative packaging techniques that support miniaturization, higher speed, greater bandwidth, lower power consumption, and reduced latency.
Innovation Solution
The development of an interconnect structure that includes through-substrate vias (TSVs) and integrated passive devices (IPDs) such as deep-trench capacitors, which are formed using advanced photolithographic and etching processes, and connected via conductive layers to provide efficient electrical connections and reduce resistance, allowing for the stacking and bonding of semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional bonding processes are used to assemble semiconductor devices, then the manufacturing process is simple, but the device size cannot be further reduced and packaging efficiency is insufficient
Solution Approach 1:
The patent transitions from traditional planar packaging to three-dimensional stacked packaging, where semiconductor devices are bonded vertically in multiple layers. This dimensional change enables significant reduction in device footprint area while accommodating multiple functional layers, directly addressing the need for further size reduction beyond traditional packaging limits
Solution Approach 2:
The patent implements nested packaging structures where smaller semiconductor devices or functional components are integrated within or between larger device layers. This nesting approach maximizes space utilization and enables higher integration density, allowing multiple devices to coexist in a compact volume
2Quantity of substance
If minimum feature size is continuously reduced to increase integration density, then more components can be integrated, but manufacturing precision requirements increase and process control becomes more difficult
Solution Approach 1:
The patent divides the semiconductor device into multiple discrete layers or modules that can be manufactured separately at relaxed precision requirements, then bonded together. This segmentation allows each layer to be optimized independently, avoiding the need for ultra-precise monolithic fabrication while achieving high overall integration density through vertical stacking
3Volume of moving object
If stacked and bonded semiconductor devices are used to reduce physical size, then device miniaturization is achieved, but bonding process complexity and sophistication increase
Solution Approach 1:
The patent incorporates bonding pads, alignment features, and electrical interconnect structures into the semiconductor devices during their respective fabrication processes before the stacking operation. This preliminary preparation of bonding interfaces simplifies the subsequent bonding process by eliminating the need for complex post-bonding alignment and connection procedures, reducing overall process sophistication requirements
Data Source
AI summary
A device includes a redistribution structure, a semiconductor device on the redistribution structure, a top package over the semiconductor device, the top package including a second semiconductor device, a molding compound interposed between the redistribution structure and the top package, a set of through vias between and electrically connecting the top package to the redistribution structure, and an interconnect structure disposed within the molding compound and electrically connecting the top package to the redistribution structure, the interconnect structure including a substrate and a passive device formed in the substrate, wherein the interconnect structure is free of active devices.