Stacked Semiconductor Isolator Coil Overlap
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Solution Overview
Problem
Current semiconductor devices with isolators face challenges in miniaturization due to the impact of wiring and elements on the Q factor of coils, leading to increased size and cost, and the need for efficient signal transmission between electrically insulated circuit blocks.
Innovation Solution
The semiconductor device employs magnetic coupling between coils on different semiconductor chips, with a specific arrangement that minimizes the influence of wiring and elements on the Q factor, allowing for a compact design and efficient signal transmission across different voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If coils are arranged to face each other on separate semiconductor chips for magnetic coupling, then signal transmission between electrically insulated circuit blocks is achieved, but the device area increases
Solution Approach 1:
The patent places the first coil in a coil formation region that overlaps with the circuit region of the first semiconductor chip, and the second coil in a coil formation region that overlaps with the circuit region of the second semiconductor chip. This nested arrangement allows the coils to be positioned vertically above each other through the substrate thickness, enabling magnetic coupling while minimizing the horizontal device area footprint.
Solution Approach 2:
The patent transitions from a planar arrangement to a three-dimensional arrangement by positioning the first and second coils on opposite sides of the substrate with their coil formation regions overlapping in plan view. This vertical stacking approach utilizes the third dimension (substrate thickness direction) to achieve magnetic coupling without increasing the lateral device area.
2Productivity
If wiring and elements are placed under coils for circuit integration, then manufacturing efficiency is improved, but the Q factor of the coils deteriorates
Solution Approach 1:
The patent designates specific coil formation regions where coils are positioned to overlap with circuit regions in plan view. Within these localized regions, the wiring and elements are strategically arranged to minimize their impact on the coil's magnetic field, thereby maintaining high Q factor while still allowing circuit integration in the overlapping areas.
Solution Approach 2:
The patent introduces an insulating film between the coil and the underlying wiring/elements in the multilayer wiring structure. This intermediary layer reduces the harmful interaction between the coil's magnetic field and the conductive wiring below, preserving the Q factor while enabling efficient signal transmission through the integrated circuit structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a more compact semiconductor device with improved reliability and reduced cost, enabling efficient signal transfer between chips with different voltage levels without significant degradation of the Q factor at operating frequencies.
Implementation Method 1
a first coil and a second coil formed in a first semiconductor chip and a second semiconductor chip respectively are arranged in a manner to face each other so as to be magnetically coupled during operation of the semiconductor device
Implementation Method 2
a third coil and a fourth coil are arranged in a multilayer wiring layer of a semiconductor chip in a manner to face each other so as to be magnetically coupled during operation of the semiconductor device
Data Source
AI summary
A compact semiconductor device with an isolator. The semiconductor device includes two chips, namely a first semiconductor chip and a second semiconductor chip which are stacked with the main surfaces of the semiconductor chips partially facing each other. A first coil and a second coil which are formed in the first semiconductor chip and the second semiconductor chip respectively are arranged to face each other so as to be magnetically coupled during operation of the semiconductor device. The pair of first and second coils make up an isolator. The first coil is arranged in a manner to overlap part of the circuit region of the first semiconductor chip in plan view and the second coil is arranged in a manner to overlap part of the circuit region of the second semiconductor chip in plan view.