Stacked Semiconductor Apparatus Yield via KGD Selection and Resin Cushioning
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Solution Overview
Problem
The existing electronic apparatuses have a reduced yield due to the stacking of non-KGD (Known Good Die) semiconductor chips on a wiring substrate, and the packaging process, particularly the high pressure and temperature during sealing resin formation, often result in semiconductor chip breakage.
Innovation Solution
The solution involves performing WLP packaging and electrical and functional inspections to identify KGD semiconductor chips, which are then stacked on a wiring substrate with resin layers and wiring patterns, and subsequently sealed with a resin, thereby enhancing resistance to packaging process pressures and temperatures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If non-KGD semiconductor chips are stacked on a wiring substrate, then the quantity of semiconductor chips can be increased, but the yield of electronic apparatus is reduced due to chip breakage during packaging
Solution Approach 1:
The patent performs WLP packaging and functional inspections on semiconductor chips before stacking them on the wiring substrate. This preliminary action ensures that only KGD (Known Good Die) chips are selected and prepared in advance, making them resistant to breakage during the subsequent sealing resin formation process. The inspection and selection occur before the stacking operation, preventing defective chips from being processed further.
Solution Approach 2:
The patent applies a resin layer to the semiconductor chips before stacking, which provides protective cushioning during the sealing resin formation process. This beforehand cushioning protects the chips from breakage caused by high pressure and temperature during packaging, ensuring higher yield when processing multiple stacked chips.
2Ease of manufacture
If high pressure and temperature are applied during sealing resin formation, then the sealing process can be completed, but semiconductor chips break due to the packaging process conditions
Solution Approach 1:
The patent performs WLP packaging on semiconductor chips before stacking, which strengthens the chips in advance. This preliminary packaging process makes the chips more resistant to the high pressure and temperature conditions during the sealing resin formation process, reducing breakage while maintaining ease of manufacture.
Solution Approach 2:
The patent applies a protective resin layer to semiconductor chips before stacking and sealing. This beforehand cushioning provides mechanical protection during the sealing process, allowing high pressure and temperature to be applied for complete sealing while preventing chip breakage.
3Reliability
If functional inspections are performed on semiconductor chips, then only KGD chips can be identified and stacked, but the manufacturing process time increases
Solution Approach 1:
The patent combines multiple inspections (electrical tests and functional inspections) into a single integrated inspection process before stacking. This merging of inspection activities ensures that only KGD chips are identified while optimizing the inspection workflow to minimize the time loss in the manufacturing process.
Solution Approach 2:
The patent performs all necessary inspections on semiconductor chips before stacking them on the wiring substrate. This preliminary action ensures that only functional KGD chips are selected in advance, preventing the need for rework or replacement later, which would consume more time overall.
Data Source
AI summary
There are provided a plurality of semiconductor apparatuses judged as good items in electrical and functional inspections while having internal connection terminals disposed on electrode pads of semiconductor chips, resin layers which are disposed on surfaces of the semiconductor chips in which the electrode pads are formed and expose the internal connection terminals, and wiring patterns which are disposed on the resin layers and are connected to the internal connection terminals, a wiring substrate on which the plurality of semiconductor apparatuses are stepwise stacked, the wiring substrate electrically connected to the plurality of semiconductor apparatuses, and a sealing resin with which the plurality of semiconductor apparatuses are sealed.