Stacked Semiconductor Lead Layout for Low Parasitic Inductance
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Solution Overview
Problem
Existing semiconductor devices with multiple elements face challenges in reducing parasitic inductance and parasitic resistance, which affect energy efficiency and switching responsiveness in power circuits.
Innovation Solution
A semiconductor device design featuring two semiconductor elements and a control element, where the leads are arranged to overlap each other, reducing the separation distance and parasitic inductance, and incorporating a lead frame and connection members to minimize parasitic resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor elements are packaged together in a conventional layout, then the device integrates multiple functions, but the parasitic inductance and parasitic resistance increase
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked configuration where semiconductor elements are arranged vertically across multiple layers. Leads extend in the thickness direction to connect elements on different substrates, enabling spatial separation of high-current power paths and control signal paths. This dimensional change reduces parasitic inductance by minimizing loop areas and reduces parasitic resistance by providing multiple parallel conduction paths through the stack.
Solution Approach 2:
The patent divides the semiconductor device into multiple independent functional modules, each housed on separate substrates within the package. Power semiconductor elements are segmented from control elements, with dedicated lead paths for each function. This segmentation allows optimization of each module's electrical characteristics independently, reducing overall parasitic effects by separating high-current paths from low-current control paths.
2Object-affected harmful factors
If semiconductor elements are placed close together to reduce parasitic inductance, then parasitic inductance decreases, but heat management becomes more difficult
Solution Approach 1:
The patent utilizes the thickness direction (z-axis) to separate heat-generating power elements from control elements by placing them on different substrates at different vertical positions. Thermal management structures can be independently designed for each layer, with heat sinks or thermal vias positioned optimally for each element without interfering with adjacent components. This vertical stacking enables effective heat dissipation while maintaining compact horizontal footprint.
Solution Approach 2:
The device is segmented into thermally isolated zones through separate substrates and lead structures. Each semiconductor element has its own thermal management pathway through the lead frame and substrate stack. This segmentation prevents heat accumulation from one element from adversely affecting adjacent elements, allowing high-power elements to be positioned close to control elements without compromising thermal performance.
3Ease of manufacture
If leads are arranged in a conventional non-overlapping pattern, then manufacturing is simpler, but parasitic resistance increases
Solution Approach 1:
The patent extends leads in the thickness direction to create overlapping projections when viewed from the top surface. This vertical arrangement allows multiple leads to occupy the same horizontal footprint without physical interference, reducing the horizontal distance current must travel and thereby reducing parasitic resistance. The overlapping configuration is achieved through precise positioning of leads on different substrate layers during the stacking process.
Solution Approach 2:
The patent merges multiple lead functions into a compact overlapping arrangement where control leads and power leads share the same horizontal space at different vertical levels. This merging reduces the overall lead length and number of external connections required, minimizing parasitic resistance while maintaining manufacturability through standardized lead frame designs that accommodate the overlapping pattern.
Data Source
AI summary
A semiconductor device provided with first and second semiconductor element each having an obverse and a reverse surface with a drain electrode, source electrode and gate electrode provided on the obverse surface. The semiconductor device is also provided with a control element electrically connected to the gate electrodes of the respective semiconductor elements, and with a plurality of leads, which include a first lead carrying the first semiconductor element, a second lead carrying the second semiconductor element, and a third lead carrying the control element. The first and second leads overlap with each other as viewed in a first direction perpendicular to the thickness direction of the semiconductor device, and the third lead overlaps with the first and second leads as viewed in a second direction perpendicular to the thickness direction and the first direction.