Stacked Semiconductor Device Linking Interconnects
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Solution Overview
Problem
The challenge in fabricating stacked semiconductor devices is the increased height and complexity in achieving thinner, more compact configurations due to the protrusion of wiring boards and the limitations in connecting bump electrodes, which hinder the realization of higher integration and smaller sizes.
Innovation Solution
A stacked semiconductor device design where a wiring board with prescribed patterns on both surfaces has exposed wiring projections covered by an encapsulant, with linking interconnects extending from the surface and over the encapsulant to connect external electrode terminals, allowing for thinner and more compact configurations by overlaying solder balls on these interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a substrate for stacking is arranged in between to connect upper and lower semiconductor devices with solder balls, then electrical connection between devices is achieved, but the height of the stacked semiconductor devices increases
Solution Approach 1:
The patent transitions from vertical stacking with intermediate substrates to a planar arrangement where semiconductor devices are positioned adjacent to each other on the same wiring board. Linking interconnects extend horizontally over the encapsulant surface to connect external electrode terminals, eliminating the need for vertical height increase while maintaining electrical connectivity.
Solution Approach 2:
The patent removes the intermediate substrate from the stacking structure. Instead of using a separate substrate to hold solder balls for vertical connection, the wiring board itself provides the connection path through linking interconnects that extend over the encapsulant, simplifying the structure and reducing height.
2Reliability
If the peripheral portion of the wiring board protrudes to expose wiring for connection with external electrode terminals, then electrical connection is enabled, but the device size increases
Solution Approach 1:
The patent moves the connection path from the peripheral horizontal extension to the vertical dimension by having linking interconnects extend over the encapsulant surface. This allows the wiring board perimeter to be compact while still providing adequate connection paths through the interconnect structure.
Solution Approach 2:
The patent combines the encapsulant structure with the connection function. The linking interconnects are integrated over the encapsulant surface, merging the protective encapsulation with the electrical connection path, thereby eliminating the need for separate peripheral wiring extensions.
3Quantity of substance
If multiple semiconductor chips are stacked on the package of the lower semiconductor device, then integration density increases, but the package height increases
Solution Approach 1:
The patent arranges semiconductor chips in a planar configuration adjacent to each other on the wiring board rather than stacking them vertically. This lateral arrangement maintains high integration density while keeping the package height compact, as connections are made through linking interconnects extending over the encapsulant rather than through vertical bump electrodes.
Data Source
AI summary
A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of insulating plastic that covers the semiconductor chip and the connection means, a plurality of electrodes formed overlying the wiring of a second surface of the wiring board, and a plurality of linking interconnects each having a portion connected to the wiring of the first surface of the wiring board and another portion exposed on the surface of the encapsulant; and an upper semiconductor device in which each electrode overlies and is electrically connected to the exposed portions of each of the linking interconnects of the lower semiconductor device. The linking interconnects extend from the first surface of the wiring board to the side surfaces and upper surface of the encapsulant, and moreover, electrically connect with wiring of the wiring board that projects from the encapsulant.