Multi-Layered Semiconductor Device With Stacked Logic And Memory
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Solution Overview
Problem
The complexity in manufacturing system-on-chip (SoC) memory devices with both high voltage and low voltage circuits in a single-layered structure, due to the difficulty in ensuring uniform gate oxide layer thicknesses and scaling down the device size to accommodate various memory circuit requirements.
Innovation Solution
A multi-layered semiconductor device structure with separate layers for logic and memory circuits, where the gate insulation layers of different thicknesses are formed on distinct substrates and connected via conductive vias, allowing for easier manufacturing and scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single-layered structure is used to integrate high voltage and low voltage circuits, then device integration is achieved, but manufacturing complexity increases and uniformity of gate oxide layers cannot be ensured
Solution Approach 1:
The device is divided into two separate layers: a first layer containing the high voltage circuit and a second layer containing the low voltage circuit. Each layer can be manufactured independently with optimized gate oxide thickness for its specific voltage requirements, eliminating the manufacturing complexity of forming different thickness oxides on a single layer while maintaining full device integration through vertical stacking and inter-layer vias.
2Adaptability or versatility
If gate oxide layers of different thicknesses are formed on a single substrate, then both high voltage and low voltage circuits are accommodated, but uniformity of oxide layers deteriorates
Solution Approach 1:
By separating high voltage and low voltage circuits into different layers, each layer can have a uniform gate oxide thickness optimized for its voltage class. The first layer has a first gate oxide thickness suitable for high voltage operation, while the second layer has a second gate oxide thickness suitable for low voltage operation, with each layer manufactured independently to ensure uniformity.
3Adaptability or versatility
If a single-layered SoC structure is used, then device functionality is integrated, but scalability to various memory sizes is limited
Solution Approach 1:
The memory device is structured with a first layer for high voltage memory circuits and a second layer for low voltage logic circuits, allowing independent optimization and scaling of each layer. This multi-layer architecture enables flexible configuration of memory capacity by adjusting the area allocated to the first layer without affecting the second layer, thereby improving scalability to various memory sizes while maintaining full device functionality.
Data Source
AI summary
A semiconductor device has a first semiconductor layer including a first circuit, a second semiconductor layer disposed on the first semiconductor layer and having a second circuit, and a via extending through portions of the first and second semiconductor layers and by which the first and second circuits are electrically connected. One of the circuits is a logic circuit and the other of the circuits is a memory circuit. The semiconductor device is manufactured by fabricating transistors of the logic and memory circuits on respective substrates, stacking the substrates, and electrically connecting the logic and memory circuits with a via.